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this document contains information on a product under development at fasl llc. the information is intended to help you evaluate this product. fasl llc reserves the right to change or discontinue work on this proposed product without notice. publication number 27631 revision a amendment 4 issue date may 13, 2004 advance information s29glxxxn mirrorbit tm flash family S29GL512N, s29gl256n, s29gl128n 512 megabit, 256 megabit, and 128 megabit, 3.0 volt-only page mode flash memory featuring 110 nm mirrorbit process technology datasheet distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? enhanced versatilei/o ? control ? all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? manufactured on 110 nm mirrorbit process technology ? secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? S29GL512N: five hundred twelve 64 kword (128 kbyte) sectors ? s29gl256n: two hundred fifty-six 64 kword (128 kbyte) sectors ? s29gl128n: one hundred twenty-eight 64 kword (128 kbyte) sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? 100,000 erase cycles per sector typical ? 20-year data retention typical performance characteristics ? high performance ? 80 ns access time (s29gl128n, s29gl256n), 90 ns access time (S29GL512N) ? 8-word/16-byte page read buffer ?25 ns page read times ? 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 25 ma typical active read current; ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options ?56-pin tsop ? 64-ball fortified bga software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? unlock bypass program command reduces overall multiple-word or byte programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? advanced sector protection ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion
2 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information general description the s29gl512/256/128n family of devices are 3.0v single power flash memory manufactured using 110 nm mirrorbit technology. the S29GL512N is a 512 mbit, organized as 33,554,432 words or 67,108,864 bytes. the s29gl256n is a 256 mbit, organized as 16,777,216 words or 33,554,432 bytes. the s29gl128n is a 128 mbit, organized as 8,388,608 words or 16,777,216 bytes. the devices have a 16-bit wide data bus that can also func tion as an 8-bit wide data bus by using the byte# input. the device can be programmed either in the host system or in standard eprom programmers. access times as fast as 80 ns (s29gl128n, s29gl256n) or 90 ns (S29GL512N) are available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide and the ordering information (512 mb) sections. the devices are offered in a 56- pin tsop or 64-ball fortified bga package. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program ( wp#/ acc) input provides shorter programming times through increased cur- rent. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the devices are entirely command set compatible with the jedec single- power-supply flash standard . commands are written to the device using standard microprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. the enhanced versatilei/o? (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on all input levels (address, chip control, and dq input levels) to the same voltage level that is asserted on the v io pin. this allows the device to operate in a 1.8 v or 3 v system environ- ment as required. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. persistent sector protection provides in-system, command-enabled protection of any combina- tion of sectors using a single power supply at v cc . password sector protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume fea- ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 3 advance information the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the host system to read bo ot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. the write protect (wp#/acc) feature protects the first or last sector by as- serting a logic low on the wp# pin. mirrorbit flash technology combines years of flash memory manufacturing expe- rience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 4 advance information table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . .6 S29GL512N ..............................................................................................................6 s29gl256n .............................................................................................................6 s29gl128n ..............................................................................................................6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .8 special package handling instructions ............................................................9 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 S29GL512N ......................................................................................................... 11 s29gl256n ........................................................................................................ 11 s29gl128n ........................................................................................................ 11 ordering information (512 mb) . . . . . . . . . . . . . . . 12 ordering information (256 mb) . . . . . . . . . . . . . . . 13 ordering information (128 mb) . . . . . . . . . . . . . . . 14 device bus operations . . . . . . . . . . . . . . . . . . . . . . 15 table 1. device bus operations ........................................... 15 word/byte configuration .................................................................................15 versatileio tm (v io ) control ..............................................................................15 requirements for reading array data ......................................................... 16 page mode read .............................................................................................. 16 writing commands/command sequences ................................................. 16 write buffer ......................................................................................................17 accelerated program operation ................................................................17 autoselect functions ......................................................................................17 standby mode ........................................................................................................17 automatic sleep mode .......................................................................................17 reset#: hardware reset pin ......................................................................... 18 output disable mode ........................................................................................ 18 table 2. sector address table?S29GL512N ........................... 18 table 3. sector address table?s29gl256n ........................... 33 table 4. sector address table?s29gl128n ........................... 40 autoselect mode ................................................................................................ 44 table 5. autoselect codes, (high voltage method) ................ 45 sector protection ................................................................................................45 persistent sector protection .......................................................................45 password sector protection ........................................................................45 wp# hardware protection .........................................................................45 selecting a sector protection mode .........................................................45 advanced sector protection .......................................................................... 46 lock register ....................................................................................................... 46 table 6. lock register ........................................................ 47 persistent sector protection ...........................................................................47 dynamic protection bit (dyb) ...................................................................47 persistent protection bit (ppb) ................................................................. 48 persistent protection bit lock (ppb lock bit) ..................................... 49 table 7. sector protection schemes ..................................... 49 persistent protection mode lock bit .......................................................... 49 password sector protection ........................................................................... 50 password and password protection mode lock bit ............................... 50 64-bit password ....................................................................................................51 persistent protection bit lock (ppb lock bit) ............................................51 secsi (secured silicon) sector flash memory region ...............................51 write protect (wp#) ........................................................................................53 hardware data protection ..............................................................................53 low vcc write inhibit ................................................................................53 write pulse ?glitch? protection ................................................................53 logical inhibit ...................................................................................................53 power-up write inhibit ................................................................................53 common flash memory interface (cfi) . . . . . . . 53 table 9. system interface string.......................................... 55 command definitions . . . . . . . . . . . . . . . . . . . . . . 57 reading array data ........................................................................................... 58 reset command ................................................................................................. 58 autoselect command sequence ................................................................... 58 enter secsi sector/exit secsi sector command sequence ................... 59 word program command sequence .......................................................... 59 unlock bypass command sequence ........................................................60 write buffer programming .........................................................................60 accelerated program ..................................................................................... 61 figure 1. write buffer programming operation....................... 63 figure 2. program operation ............................................... 64 program suspend/program resume command sequence .................... 64 figure 3. program suspend/program resume ........................ 65 chip erase command sequence ................................................................... 65 sector erase command sequence ................................................................ 66 figure 4. erase operation ................................................... 67 erase suspend/erase resume commands .................................................. 67 lock register command set definitions ....................................................68 password protection command set definitions ......................................68 non-volatile sector protection command set definitions .................. 70 global volatile sector protection freeze command set ...................... 70 volatile sector protection command set ................................................... 71 secsi sector entry command .......................................................................... 71 secsi sector exit command ........................................................................... 72 command definitions ........................................................................................ 73 table 12. S29GL512N, s29gl256n, s29gl128n command defini- tions, x16 ......................................................................... 73 table 13. S29GL512N, s29gl256n, s29gl128n command defini- tions, x8 ........................................................................... 76 write operation status ................................................................................... 78 dq7: data# polling ........................................................................................... 78 figure 5. data# polling algorithm ........................................ 80 ry/by#: ready/busy# .......................................................................................80 dq6: toggle bit i ................................................................................................ 81 figure 6. toggle bit algorithm ............................................. 82 dq2: toggle bit ii .............................................................................................. 82 reading toggle bits dq6/dq2 ..................................................................... 83 dq5: exceeded timing limits ........................................................................ 83 dq3: sector erase timer ................................................................................ 83 dq1: write-to-buffer abort ...........................................................................84 table 14. write operation status ......................................... 84 figure 7. maximum negative overshoot waveform................. 85 figure 8. maximum positive overshoot waveform.......................................................... 85 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 85 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 86 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 9. test setup........................................................... 87 table 15. test specifications ............................................... 87 key to switching waveforms . . . . . . . . . . . . . . . . 87 figure 10. input waveforms and measurement levels........................................................... 87 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 88 read-only operations?S29GL512N only ..................................................88 read-only operations?s29gl256n only .................................................89 read-only operations?s29gl128n only ..................................................90 figure 11. read operation timings....................................... 91 figure 12. page read timings.............................................. 91
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 5 advance information hardware reset (reset#) .............................................................................. 92 figure 13. reset timings ..................................................... 92 erase and program operations?S29GL512N only ...................................93 erase and program operations?s29gl256n only ................................. 94 erase and program operations?s29gl128n only ...................................95 figure 14. program operation timings .................................. 96 figure 15. accelerated program timing diagram .................... 96 figure 16. chip/sector erase operation timings ..................... 97 figure 17. data# polling timings (during embedded algorithms) ............................................ 98 figure 18. toggle bit timings (during embedded algorithms) .. 99 figure 19. dq2 vs. dq6 ...................................................... 99 alternate ce# controlled erase and program operations? S29GL512N only ...............................................................................................100 alternate ce# controlled erase and program operations? s29gl256n only ................................................................................................101 alternate ce# controlled erase and program operations? s29gl128n only ...............................................................................................102 figure 20. alternate ce# controlled write (erase/program) operation timings............................................................ 103 erase and programming performance . . . . . . . 104 tsop pin and bga package capacitance . . . . 104 physical dimensions . . . . . . . . . . . . . . . . . . . . . . .105 ts056?56-pin standard thin small outline package (tsop) ............105 laa064?64-ball fortified ball grid array (fbga) ..............................106 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 107
6 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information product selector guide S29GL512N s29gl256n s29gl128n part number S29GL512N speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 90 10 v io = 1.65?1.95 v 10 11 max. access time (ns) 90 100 100 110 max. ce# access time (ns) 90 100 100 110 max. page access time (ns) 25 25 35 35 max. oe# access time (ns) 25 25 35 35 part number s29gl256n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 80 90 v io = 1.65?1.95 v 90 10 max. access time (ns) 80 90 90 100 max. ce# access time (ns) 80 90 90 100 max. page access time (ns) 25 25 35 35 max. oe# access time (ns) 25 25 35 35 part number s29gl128n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 80 90 v io = 1.65?1.95 v 90 10 max. access time (ns) 80 90 90 100 max. ce# access time (ns) 80 90 90 100 max. page access time (t pacc )25253535 max. oe# access time (ns) 25 25 35 35
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 7 advance information block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0 ** a max gl512n = a24, a max gl256n = a23, a max gl128n = a22
8 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 a24 nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io nc for s29gl256n and s29gl128n nc for s29gl128n 56-pin standard tsop
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 9 advance information connection diagrams note: 1. ball c8 is nc on s29gl128n 2. ball f8 is nc on s29gl256n and s29gl128n special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga). the package and/or data integrity may be compromised if the pack- age body is exposed to temperatures above 150 c for prolonged periods of time. a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc a24 2 v ss v io a23 1 a22 nc 64-ball fortified bga top view, balls facing down
10 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information pin description a24?a0 = 25 address inputs (512 mb) a23?a0 = 24 address inputs (256 mb) a22?a0 = 23 address inputs (128 mb) dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input; acceleration input reset# = hardware reset pin input byte# = selects 8-bit or 16-bit mode ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v io = output buffer power v ss = device ground nc = pin not connected internally
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 11 advance information logic symbol S29GL512N s29gl256n s29gl128n 25 16 or 8 dq15?dq0 (a-1) a24?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte# 24 16 or 8 dq15?dq0 (a-1) a23?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte# 23 16 or 8 dq15?dq0 (a-1) a22?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte#
12 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ordering information (512 mb) the ordering part number is formed by a valid combination of the following: notes: 1. type 0 is standard. specify other options as required. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading ?s29? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29GL512N 10 f a i 00 0 packing type 0 = tray (standard; see note 1) 3 = 13? tape and reel model number (v io range, protection when wp# =v il ) 01 = v io = 2.7 to 3.6 v, highest address sector protected 02 = v io = 2.7 to 3.6 v, lowest address sector protected l v1 = v io = 1.65 to 1.95 v, highest address sector protected v2 = v io = 1.65 to 1.95 v, lowest address sector protected temperature range i = industrial (?40 c to +85 c) package materials set a= standard f= pb-free package type t = thin small outline package (tsop) standard pinout f = fortified ball grid array, 1.0 mm pitch package speed option 90 = 90 ns 10 = 100 ns 11 = 110 ns device number/description S29GL512N 3.0 volt-only, 512 megabit (32 m x 16-bit/64 m x 8-bit) page-mode flash memory manufactured on 110 nm mirrorbit tm process technology S29GL512N valid combinations package description 512 mb speed (ns) package & temperature model number pack type S29GL512N 90, 10 tai, tfi fai, ffi 01, 02 0, 3 (note 1) ts056 (note 2) tsop 10, 11 v1, v2 laa064 (note 3) fortified bga
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 13 advance information ordering information (256 mb) the ordering part number is formed by a valid combination of the following: notes: 1. type 0 is standard. specify other options as required. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading ?s29? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29gl256n 90 t a i 00 0 packing type 0 = tray (standard; see note 1) 3 = 13? tape and reel model number (v io range, protection when wp# =v il ) 01 = v io = 2.7 to 3.6 v, highest address sector protected 02 = v io = 2.7 to 3.6 v, lowest address sector protected l v1 = v io = 1.65 to 1.95 v, highest address sector protected v2 = v io = 1.65 to 1.95 v, lowest address sector protected temperature range i = industrial (?40 c to +85 c) package materials set a= standard f= pb-free package type t = thin small outline package (tsop) standard pinout f = fortified ball grid array, 1.0 mm pitch package speed option 80 = 80 ns 90 = 90 ns 10 = 100 ns device number/description s29gl256n 3.0 volt-only, 256 megabit (16 m x 16-bit/64 m x 8-bit) page-mode flash memory manufactured on 110 nm mirrorbit tm process technology S29GL512N valid combinations package description 256 mb speed (ns) package & temperature model number pack type s29gl256n 80, 90 tai, tfi fai, ffi 01, 02 0, 2 (note 1) ts056 (note 2) tsop 90, 10 v1, v2 laa064 (note 3) fortified bga
14 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ordering information (128 mb) the ordering part number is formed by a valid combination of the following: notes: 1. type 0 is standard. specify other options as required. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading ?s29? and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29gl128n 90 t a i 00 0 packing type 0 = tray (standard; see note 1) 3 = 13? tape and reel model number (v io range, protection when wp# =v il ) 01 = v io = 2.7 to 3.6 v, highest address sector protected 02 = v io = 2.7 to 3.6 v, lowest address sector protected l v1 = v io = 1.65 to 1.95 v, highest address sector protected v2 = v io = 1.65 to 1.95 v, lowest address sector protected temperature range i = industrial (?40 c to +85 c) package materials set a= standard f= pb-free package type t = thin small outline package (tsop) standard pinout f = fortified ball grid array, 1.0 mm pitch package speed option 80 = 80 ns 90 = 90 ns 10 = 100 ns device number/description s29gl128n 3.0 volt-only, 512 megabit (32 m x 16-bit/64 m x 8-bit) page-mode flash memory manufactured on 110 nm mirrorbit tm process technology S29GL512N valid combinations package description 128 mb speed (ns) package & temperature model number pack type s29gl128n 80, 90 tai, tfi fai, ffi 01, 02 0, 3 (note 1) ts056 (note 2) tsop 90, 10 v1, v2 laa064 (note 3) fortified bga
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 15 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state mach ine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the fo llowing subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are amax:a0 in word mode; a max :a-1 in byte mode. sector addresses are a max :a16 in both modes. 2. if wp# = v il , the first or last sector group remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 3. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word con- figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/ o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. versatileio tm (v io ) control the versatileio tm (v io ) control allows the host system to set the voltage levels that the device generates and tolerates on ce# and dq i/os to the same voltage operation ce# oe# we # reset# wp#/ acc addresses (note 2) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h note 2 a in (note 3) (note 3) accelerated program l h l h v hh a in (note 3) (note 3) standby v cc 0.3 v xx v cc 0.3 v h x high-z high-z high-z output disable l h h h x x high-z high-z high-z reset x x x l x x high-z high-z high-z
16 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information level that is asserted on v io . see ordering information for v io options on this device. for example, a v i/o of 1.65?3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 v devices on the same data bus. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only op- erations table for timing specifications and to figure 11 for the timing diagram. refer to the dc characteristics table for the active current specification on read- ing array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a(max)?a3. address bits a2?a0 in word mode (a2?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is de-asserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypa ss mode, only two write cycles are re- quired to program a word or byte, instead of four. the ?word/byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. table 2 indicates the address space that each sector occupies.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 17 advance information refer to the dc characteristics table for the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the afore- mentioned unlock bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command se- quence as required by the un lock bypass mode. removing v hh from the wp#/ acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device dam- age may result. wp# has an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect comm and sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? section on page 44 and ?autoselect command sequence? section on page 58 sections for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high im pedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during eras ure or programming, the device draws ac- tive current until the operation is completed. refer to the ?dc characteristics? sect ion on page 86 for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de- vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con-
18 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the ?dc characteristics? section on page 86 for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the op- eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. refer to the ac characteristics tables for reset# parameters and to figure 13 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. table 2. sector address table?S29GL512N sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 000000000 128/64 0000000?001ffff 0000000?000ffff sa1 000000001 128/64 0020000?003ffff 0010000?001ffff sa2 000000010 128/64 0040000?005ffff 0020000?002ffff sa3 000000011 128/64 0060000?007ffff 0030000?003ffff sa4 000000100 128/64 0080000?009ffff 0040000?004ffff sa5 000000101 128/64 00a0000?00bffff 0050000?005ffff sa6 000000110 128/64 00c0000?00dffff 0060000?006ffff sa7 000000111 128/64 00e0000?00fffff 0070000?007ffff sa8 000001000 128/64 0100000?011ffff 0080000?008ffff sa9 000001001 128/64 0120000?013ffff 0090000?009ffff sa10 000001010 128/64 0140000?015ffff 00a0000?00affff sa11 000001011 128/64 0160000?017ffff 00b0000?00bffff sa12 000001100 128/64 0180000?019ffff 00c0000?00cffff sa13 000001101 128/64 01a0000?01bffff 00d0000?00dffff
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 19 advance information sa14 000001110 128/64 01c0000?01dffff 00e0000?00effff sa15 000001111 128/64 01e0000?01fffff 00f0000?00fffff sa16 000010000 128/64 0200000?021ffff 0100000?010ffff sa17 000010001 128/64 0220000?023ffff 0110000?011ffff sa18 000010010 128/64 0240000?025ffff 0120000?012ffff sa19 000010011 128/64 0260000?027ffff 0130000?013ffff sa20 000010100 128/64 0280000?029ffff 0140000?014ffff sa21 000010101 128/64 02a0000?02bffff 0150000?015ffff sa22 000010110 128/64 02c0000?02dffff 0160000?016ffff sa23 000010111 128/64 02e0000?02fffff 0170000?017ffff sa24 000011000 128/64 0300000?031ffff 0180000?018ffff sa25 000011001 128/64 0320000?033ffff 0190000?019ffff sa26 000011010 128/64 0340000?035ffff 01a0000?01affff sa27 000011011 128/64 0360000?037ffff 01b0000?01bffff sa28 000011100 128/64 0380000?039ffff 01c0000?01cffff sa29 000011101 128/64 03a0000?03bffff 01d0000?01dffff sa30 000011110 128/64 03c0000?03dffff 01e0000?01effff sa31 000011111 128/64 03e0000?0efffff 01f0000?01fffff sa32 000100000 128/64 0400000?041ffff 0200000?020ffff sa33 000100001 128/64 0420000?043ffff 0210000?021ffff sa34 000100010 128/64 0440000?045ffff 0220000?022ffff sa35 000100011 128/64 0460000?047ffff 0230000?023ffff sa36 000100100 128/64 0480000?049ffff 0240000?024ffff sa37 000100101 128/64 04a0000?04bffff 0250000?025ffff sa38 000100110 128/64 04c0000?04dffff 0260000?026ffff sa39 000100111 128/64 04e0000?04fffff 0270000?027ffff sa40 000101000 128/64 0500000?051ffff 0280000?028ffff sa41 000101001 128/64 0520000?053ffff 0290000?029ffff sa42 000101010 128/64 0540000?055ffff 02a0000?02affff sa43 000101011 128/64 0560000?057ffff 02b0000?02bffff sa44 000101100 128/64 0580000?059ffff 02c0000?02cffff sa45 000101101 128/64 05a0000?05bffff 02d0000?02dffff sa46 000101110 128/64 05c0000?05dffff 02e0000?02effff sa47 000101111 128/64 05e0000?05fffff 02f0000?02fffff sa48 000110000 128/64 0600000?061ffff 0300000?030ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
20 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa49 000110001 128/64 0620000?063ffff 0310000?031ffff sa50 000110010 128/64 0640000?065ffff 0320000?032ffff sa51 000110011 128/64 0660000?067ffff 0330000?033ffff sa52 000110100 128/64 0680000?069ffff 0340000?034ffff sa53 000110101 128/64 06a0000?06bffff 0350000?035ffff sa54 000110110 128/64 06c0000?06dffff 0360000?036ffff sa55 000110111 128/64 06e0000?06fffff 0370000?037ffff sa56 000111000 128/64 0700000?071ffff 0380000?038ffff sa57 000111001 128/64 0720000?073ffff 0390000?039ffff sa58 000111010 128/64 0740000?075ffff 03a0000?03affff sa59 000111011 128/64 0760000?077ffff 03b0000?03bffff sa60 000111100 128/64 0780000?079ffff 03c0000?03cffff sa61 000111101 128/64 07a0000?07bffff 03d0000?03dffff sa62 000111110 128/64 07c0000?07dffff 03e0000?03effff sa63 000111111 128/64 07e0000?07fffff 03f0000?03fffff sa64 001000000 128/64 0800000?081ffff 0400000?040ffff sa65 001000001 128/64 0820000?083ffff 0410000?041ffff sa66 001000010 128/64 0840000?085ffff 0420000?042ffff sa67 001000011 128/64 0860000?087ffff 0430000?043ffff sa68 001000100 128/64 0880000?089ffff 0440000?044ffff sa69 001000101 128/64 08a0000?08bffff 0450000?045ffff sa70 001000110 128/64 08c0000?08dffff 0460000?046ffff sa71 001000111 128/64 08e0000?08fffff 0470000?047ffff sa72 001001000 128/64 0900000?091ffff 0480000?048ffff sa73 001001001 128/64 0920000?093ffff 0490000?049ffff sa74 001001010 128/64 0940000?095ffff 04a0000?04affff sa75 001001011 128/64 0960000?097ffff 04b0000?04bffff sa76 001001100 128/64 0980000?099ffff 04c0000?04cffff sa77 001001101 128/64 09a0000?09bffff 04d0000?04dffff sa78 001001110 128/64 09c0000?09dffff 04e0000?04effff sa79 001001111 128/64 09e0000?09fffff 04f0000?04fffff sa80 001010000 128/64 0a00000?0a1ffff 0500000?050ffff sa81 001010001 128/64 0a20000?0a3ffff 0510000?051ffff sa82 001010010 128/64 0a40000?0a5ffff 0520000?052ffff sa83 001010011 128/64 0a60000?0a7ffff 0530000?053ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 21 advance information sa84 001010100 128/64 0a80000?0a9ffff 0540000?054ffff sa85 001010101 128/64 0aa0000?0abffff 0550000?055ffff sa86 001010110 128/64 0ac0000?0adffff 0560000?056ffff sa87 001010111 128/64 0ae0000?0afffff 0570000?057ffff sa88 001011000 128/64 0b00000?0b1ffff 0580000?058ffff sa89 001011001 128/64 0b20000?0b3ffff 0590000?059ffff sa90 001011010 128/64 0b40000?0b5ffff 05a0000?05affff sa91 001011011 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 001011100 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 001011101 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 001011110 128/64 0bc0000?0bdffff 05e0000?05effff sa95 001011111 128/64 0be0000?0bfffff 05f0000?05fffff sa96 001100000 128/64 0c00000?0c1ffff 0600000?060ffff sa97 001100001 128/64 0c20000?0c3ffff 0610000?061ffff sa98 001100010 128/64 0c40000?0c5ffff 0620000?062ffff sa99 001100011 128/64 0c60000?0c7ffff 0630000?063ffff sa100 001100100 128/64 0c80000?0c9ffff 0640000?064ffff sa101 001100101 128/64 0ca0000?0cbffff 0650000?065ffff sa102 001100110 128/64 0cc0000?0cdffff 0660000?066ffff sa103 001100111 128/64 0ce0000?0cfffff 0670000?067ffff sa104 001101000 128/64 0d00000?0d1ffff 0680000?068ffff sa105 001101001 128/64 0d20000?0d3ffff 0690000?069ffff sa106 001101010 128/64 0d40000?0d5ffff 06a0000?06affff sa107 001101011 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 001101100 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 001101101 128/64 0da0000?0dbffff 06d0000?06dffff sa110 001101110 128/64 0dc0000?0ddffff 06e0000?06effff sa111 001101111 128/64 0de0000?0dfffff 06f0000?06fffff sa112 001110000 128/64 0e00000?0e1ffff 0700000?070ffff sa113 001110001 128/64 0e20000?0e3ffff 0710000?071ffff sa114 001110010 128/64 0e40000?0e5ffff 0720000?072ffff sa115 001110011 128/64 0e60000?0e7ffff 0730000?073ffff sa116 001110100 128/64 0e80000?0e9ffff 0740000?074ffff sa117 001110101 128/64 0ea0000?0ebffff 0750000?075ffff sa118 001110110 128/64 0ec0000?0edffff 0760000?076ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
22 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa119 001110111 128/64 0ee0000?0efffff 0770000?077ffff sa120 001111000 128/64 0f00000?0f1ffff 0780000?078ffff sa121 001111001 128/64 0f20000?0f3ffff 0790000?079ffff sa122 001111010 128/64 0f40000?0f5ffff 07a0000?07affff sa123 001111011 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 001111100 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 001111101 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 001111110 128/64 0fc0000?0fdffff 07e0000?07effff sa127 001111111 128/64 0fe0000?0ffffff 07f0000?07fffff sa128 010000000 128/64 1000000?101ffff 0800000?080ffff sa129 010000001 128/64 1020000?103ffff 0810000?081ffff sa130 010000010 128/64 1040000?105ffff 0820000?082ffff sa131 010000011 128/64 1060000?017ffff 0830000?083ffff sa132 010000100 128/64 1080000?109ffff 0840000?084ffff sa133 010000101 128/64 10a0000?10bffff 0850000?085ffff sa134 010000110 128/64 10c0000?10dffff 0860000?086ffff sa135 010000111 128/64 10e0000?10fffff 0870000?087ffff sa136 010001000 128/64 1100000?111ffff 0880000?088ffff sa137 010001001 128/64 1120000?113ffff 0890000?089ffff sa138 010001010 128/64 1140000?115ffff 08a0000?08affff sa139 010001011 128/64 1160000?117ffff 08b0000?08bffff sa140 010001100 128/64 1180000?119ffff 08c0000?08cffff sa141 010001101 128/64 11a0000?11bffff 08d0000?08dffff sa142 010001110 128/64 11c0000?11dffff 08e0000?08effff sa143 010001111 128/64 11e0000?11fffff 08f0000?08fffff sa144 010010000 128/64 1200000?121ffff 0900000?090ffff sa145 010010001 128/64 1220000?123ffff 0910000?091ffff sa146 010010010 128/64 1240000?125ffff 0920000?092ffff sa147 010010011 128/64 1260000?127ffff 0930000?093ffff sa148 010010100 128/64 1280000?129ffff 0940000?094ffff sa149 010010101 128/64 12a0000?12bffff 0950000?095ffff sa150 010010110 128/64 12c0000?12dffff 0960000?096ffff sa151 010010111 128/64 12e0000?12fffff 0970000?097ffff sa152 010011000 128/64 1300000?131ffff 0980000?098ffff sa153 010011001 128/64 1320000?133ffff 0990000?099ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 23 advance information sa154 010011010 128/64 1340000?135ffff 09a0000?09affff sa155 010011011 128/64 1360000?137ffff 09b0000?09bffff sa156 010011100 128/64 1380000?139ffff 09c0000?09cffff sa157 010011101 128/64 13a0000?13bffff 09d0000?09dffff sa158 010011110 128/64 13c0000?13dffff 09e0000?09effff sa159 010011111 128/64 13e0000?13fffff 09f0000?09fffff sa160 010100000 128/64 1400000?141ffff 0a00000?0a0ffff sa161 010100001 128/64 1420000?143ffff 0a10000?0a1ffff sa162 010100010 128/64 1440000?145ffff 0a20000?0a2ffff sa163 010100011 128/64 1460000?147ffff 0a30000?0a3ffff sa164 010100100 128/64 1480000?149ffff 0a40000?0a4ffff sa165 010100101 128/64 14a0000?14bffff 0a50000?0a5ffff sa166 010100110 128/64 14c0000?14dffff 0a60000?0a6ffff sa167 010100111 128/64 14e0000?14fffff 0a70000?0a7ffff sa168 010101000 128/64 1500000?151ffff 0a80000?0a8ffff sa169 010101001 128/64 1520000?153ffff 0a90000?0a9ffff sa170 010101010 128/64 1540000?155ffff 0aa0000?0aaffff sa171 010101011 128/64 1560000?157ffff 0ab0000?0abffff sa172 010101100 128/64 1580000?159ffff 0ac0000?0acffff sa173 010101101 128/64 15a0000?15bffff 0ad0000?0adffff sa174 010101110 128/64 15c0000?15dffff 0ae0000?0aeffff sa175 010101111 128/64 15e0000?15fffff 0af0000?0afffff sa176 010110000 128/64 160000?161ffff 0b00000?0b0ffff sa177 010110001 128/64 1620000?163ffff 0b10000?0b1ffff sa178 010110010 128/64 1640000?165ffff 0b20000?0b2ffff sa179 010110011 128/64 1660000?167ffff 0b30000?0b3ffff sa180 010110100 128/64 1680000?169ffff 0b40000?0b4ffff sa181 010110101 128/64 16a0000?16bffff 0b50000?0b5ffff sa182 010110110 128/64 16c0000?16dffff 0b60000?0b6ffff sa183 010110111 128/64 16e0000?16fffff 0b70000?0b7ffff sa184 010111000 128/64 1700000?171ffff 0b80000?0b8ffff sa185 010111001 128/64 1720000?173ffff 0b90000?0b9ffff sa186 010111010 128/64 1740000?175ffff 0ba0000?0baffff sa187 010111011 128/64 1760000?177ffff 0bb0000?0bbffff sa188 010111100 128/64 1780000?179ffff 0bc0000?0bcffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
24 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa189 010111101 128/64 17a0000?17bffff 0bd0000?0bdffff sa190 010111110 128/64 17c0000?17dffff 0be0000?0beffff sa191 010111111 128/64 17e0000?17fffff 0bf0000?0bfffff sa192 011000000 128/64 1800000?181ffff 0c00000?0c0ffff sa193 011000001 128/64 1820000?183ffff 0c10000?0c1ffff sa194 011000010 128/64 1840000?185ffff 0c20000?0c2ffff sa195 011000011 128/64 1860000?187ffff 0c30000?0c3ffff sa196 011000100 128/64 1880000?189ffff 0c40000?0c4ffff sa197 011000101 128/64 18a0000?18bffff 0c50000?0c5ffff sa198 011000110 128/64 18c0000?18dffff 0c60000?0c6ffff sa199 011000111 128/64 18e0000?18fffff 0c70000?0c7ffff sa200 011001000 128/64 1900000?191ffff 0c80000?0c8ffff sa201 011001001 128/64 1920000?193ffff 0c90000?0c9ffff sa202 011001010 128/64 1940000?195ffff 0ca0000?0caffff sa203 011001011 128/64 1960000?197ffff 0cb0000?0cbffff sa204 011001100 128/64 1980000?199ffff 0cc0000?0ccffff sa205 011001101 128/64 19a0000?19bffff 0cd0000?0cdffff sa206 011001110 128/64 19c0000?19dffff 0ce0000?0ceffff sa207 011001111 128/64 19e0000?19fffff 0cf0000?0cfffff sa208 011010000 128/64 1a00000?1a1ffff 0d00000?0d0ffff sa209 011010001 128/64 1a20000?1a3ffff 0d10000?0d1ffff sa210 011010010 128/64 1a40000?1a5ffff 0d20000?0d2ffff sa211 011010011 128/64 1a60000?1a7ffff 0d30000?0d3ffff sa212 011010100 128/64 1a80000?1a9ffff 0d40000?0d4ffff sa213 011010101 128/64 1aa0000?1abffff 0d50000?0d5ffff sa214 011010110 128/64 1ac0000?1adffff 0d60000?0d6ffff sa215 011010111 128/64 1ae0000?1afffff 0d70000?0d7ffff sa216 011011000 128/64 1b00000?1b1ffff 0d80000?0d8ffff sa217 011011001 128/64 1b20000?1b3ffff 0d90000?0d9ffff sa218 011011010 128/64 1b40000?1b5ffff 0da0000?0daffff sa219 011011011 128/64 1b60000?1b7ffff 0db0000?0dbffff sa220 011011100 128/64 1b80000?1b9ffff 0dc0000?0dcffff sa221 011011101 128/64 1ba0000?1bbffff 0dd0000?0ddffff sa222 011011110 128/64 1bc0000?1bdffff 0de0000?0deffff sa223 011011111 128/64 1be0000?1bfffff 0df0000?0dfffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 25 advance information sa224 011100000 128/64 1c00000?1c1ffff 0e00000?0e0ffff sa225 011100001 128/64 1c20000?1c3ffff 0e10000?0e1ffff sa226 011100010 128/64 1c40000?1c5ffff 0e20000?0e2ffff sa227 011100011 128/64 1c60000?1c7ffff 0e30000?0e3ffff sa228 011100100 128/64 1c80000?1c9ffff 0e40000?0e4ffff sa229 011100101 128/64 1ca0000?1cbffff 0e50000?0e5ffff sa230 011100110 128/64 1cc0000?1cdffff 0e60000?0e6ffff sa231 011100111 128/64 1ce0000?1cfffff 0e70000?0e7ffff sa232 011101000 128/64 1d00000?1d1ffff 0e80000?0e8ffff sa233 011101001 128/64 1d20000?1d3ffff 0e90000?0e9ffff sa234 011101010 128/64 1d40000?1d5ffff 0ea0000?0eaffff sa235 011101011 128/64 1d60000?1d7ffff 0eb0000?0ebffff sa236 011101100 128/64 1d80000?1d9ffff 0ec0000?0ecffff sa237 011101101 128/64 1da0000?1dbffff 0ed0000?0edffff sa238 011101110 128/64 1dc0000?1ddffff 0ee0000?0eeffff sa239 011101111 128/64 1de0000?1dfffff 0ef0000?0efffff sa240 011110000 128/64 1e00000?1e1ffff 0f00000?0f0ffff sa241 011110001 128/64 1e20000?1e3ffff 0f10000?0f1ffff sa242 011110010 128/64 1e40000?1e5ffff 0f20000?0f2ffff sa243 011110011 128/64 1e60000?1e7ffff 0f30000?0f3ffff sa244 011110100 128/64 1e80000?1e9ffff 0f40000?0f4ffff sa245 011110101 128/64 1ea0000?1ebffff 0f50000?0f5ffff sa246 011110110 128/64 1ec0000?1edffff 0f60000?0f6ffff sa247 011110111 128/64 1ee0000?1efffff 0f70000?0f7ffff sa248 011111000 128/64 1f00000?1f1ffff 0f80000?0f8ffff sa249 011111001 128/64 1f20000?1f3ffff 0f90000?0f9ffff sa250 011111010 128/64 1f40000?1f5ffff 0fa0000?0faffff sa251 011111011 128/64 1f60000?1f7ffff 0fb0000?0fbffff sa252 011111100 128/64 1f80000?1f9ffff 0fc0000?0fcffff sa253 011111101 128/64 1fa0000?1fbffff 0fd0000?0fdffff sa254 011111110 128/64 1fc0000?1fdffff 0fe0000?0feffff sa255 011111111 128/64 1fe0000?1ffffff 0ff0000?0ffffff sa256 100000000 128/64 2000000?201ffff 1000000?100ffff sa257 100000001 128/64 2020000?203ffff 1010000?101ffff sa258 100000010 128/64 2040000?205ffff 1020000?102ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
26 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa259 100000011 128/64 2060000?207ffff 1030000?103ffff sa260 100000100 128/64 2080000?209ffff 1040000?104ffff sa261 100000101 128/64 20a0000?20bffff 1050000?105ffff sa262 100000110 128/64 20c0000?20dffff 1060000?106ffff sa263 100000111 128/64 20e0000?20fffff 1070000?107ffff sa264 100001000 128/64 2100000?211ffff 1080000?108ffff sa265 100001001 128/64 2120000?213ffff 1090000?109ffff sa266 100001010 128/64 2140000?215ffff 10a0000?10affff sa267 100001011 128/64 2160000?217ffff 10b0000?10bffff sa268 100001100 128/64 2180000?219ffff 10c0000?10cffff sa269 100001101 128/64 21a0000?21bffff 10d0000?10dffff sa270 100001110 128/64 21c0000?21dffff 10e0000?10effff sa271 100001111 128/64 21e0000?21fffff 10f0000?10fffff sa272 100010000 128/64 2200000?221ffff 1100000?110ffff sa273 100010001 128/64 2220000?223ffff 1110000?111ffff sa274 100010010 128/64 2240000?225ffff 1120000?112ffff sa275 100010011 128/64 2260000?227ffff 1130000?113ffff sa276 100010100 128/64 2280000?229ffff 1140000?114ffff sa277 100010101 128/64 22a0000?22bffff 1150000?115ffff sa278 100010110 128/64 22c0000?22dffff 1160000?116ffff sa279 100010111 128/64 22e0000?22fffff 1170000?117ffff sa280 100011000 128/64 2300000?231ffff 1180000?118ffff sa281 100011001 128/64 2320000?233ffff 1190000?119ffff sa282 100011010 128/64 2340000?235ffff 11a0000?11affff sa283 100011011 128/64 2360000?237ffff 11b0000?11bffff sa284 100011100 128/64 2380000?239ffff 11c0000?11cffff sa285 100011101 128/64 23a0000?23bffff 11d0000?11dffff sa286 100011110 128/64 23c0000?23dffff 11e0000?11effff sa287 100011111 128/64 23e0000?23fffff 11f0000?11fffff sa288 100100000 128/64 2400000?241ffff 1200000?120ffff sa289 100100001 128/64 2420000?243ffff 1210000?121ffff sa290 100100010 128/64 2440000?245ffff 1220000?122ffff sa291 100100011 128/64 2460000?247ffff 1230000?123ffff sa292 100100100 128/64 2480000?249ffff 1240000?124ffff sa293 100100101 128/64 24a0000?24bffff 1250000?125ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 27 advance information sa294 100100110 128/64 24c0000?24dffff 1260000?126ffff sa295 100100111 128/64 24e0000?24fffff 1270000?127ffff sa296 100101000 128/64 2500000?251ffff 1280000?128ffff sa297 100101001 128/64 2520000?253ffff 1290000?129ffff sa298 100101010 128/64 2540000?255ffff 12a0000?12affff sa299 100101011 128/64 2560000?257ffff 12b0000?12bffff sa300 100101100 128/64 2580000?259ffff 12c0000?12cffff sa301 100101101 128/64 25a0000?25bffff 12d0000?12dffff sa302 100101110 128/64 25c0000?25dffff 12e0000?12effff sa303 100101111 128/64 25e0000?25fffff 12f0000?12fffff sa304 100110000 128/64 2600000?261ffff 1300000?130ffff sa305 100110001 128/64 2620000?263ffff 1310000?131ffff sa306 100110010 128/64 2640000?265ffff 1320000?132ffff sa307 100110011 128/64 2660000?267ffff 1330000?133ffff sa308 100110100 128/64 2680000?269ffff 1340000?134ffff sa309 100110101 128/64 26a0000?26bffff 1350000?135ffff sa310 100110110 128/64 26c0000?26dffff 1360000?136ffff sa311 100110111 128/64 26e0000?26fffff 1370000?137ffff sa312 100111000 128/64 2700000?271ffff 1380000?138ffff sa313 100111001 128/64 2720000?273ffff 1390000?139ffff sa314 100111010 128/64 2740000?275ffff 13a0000?13affff sa315 100111011 128/64 2760000?277ffff 13b0000?13bffff sa316 100111100 128/64 2780000?279ffff 13c0000?13cffff sa317 100111101 128/64 27a0000?27bffff 13d0000?13dffff sa318 100111110 128/64 27c0000?27dffff 13e0000?13effff sa319 100111111 128/64 27e0000?27fffff 13f0000?13fffff sa320 101000000 128/64 2800000?281ffff 1400000?140ffff sa321 101000001 128/64 2820000?283ffff 1410000?141ffff sa322 101000010 128/64 2840000?285ffff 1420000?142ffff sa323 101000011 128/64 2860000?287ffff 1430000?143ffff sa324 101000100 128/64 2880000?289ffff 1440000?144ffff sa325 101000101 128/64 28a0000?28bffff 1450000?145ffff sa326 101000110 128/64 28c0000?28dffff 1460000?146ffff sa327 101000111 128/64 28e0000?28fffff 1470000?147ffff sa328 101001000 128/64 2900000?291ffff 1480000?148ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
28 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa329 101001001 128/64 2920000?293ffff 1490000?149ffff sa330 101001010 128/64 2940000?295ffff 14a0000?14affff sa331 101001011 128/64 2960000?297ffff 14b0000?14bffff sa332 101001100 128/64 2980000?299ffff 14c0000?14cffff sa333 101001101 128/64 29a0000?29bffff 14d0000?14dffff sa334 101001110 128/64 29c0000?29dffff 14e0000?14effff sa335 101001111 128/64 29e0000?29fffff 14f0000?14fffff sa336 101010000 128/64 2a00000?2a1ffff 1500000?150ffff sa337 101010001 128/64 2a20000?2a3ffff 1510000?151ffff sa338 101010010 128/64 2a40000?2a5ffff 1520000?152ffff sa339 101010011 128/64 2a60000?2a7ffff 1530000?153ffff sa340 101010100 128/64 2a80000?2a9ffff 1540000?154ffff sa341 101010101 128/64 2aa0000?2abffff 1550000?155ffff sa342 101010110 128/64 2ac0000?2adffff 1560000?156ffff sa343 101010111 128/64 2ae00000?2efffff 1570000?157ffff sa344 101011000 128/64 2b00000?2b1ffff 1580000?158ffff sa345 101011001 128/64 2b20000?2b3ffff 1590000?159ffff sa346 101011010 128/64 2b40000?2b5ffff 15a0000?15affff sa347 101011011 128/64 2b60000?2b7ffff 15b0000?15bffff sa348 101011100 128/64 2b80000?2b9ffff 15c0000?15cffff sa349 101011101 128/64 2ba0000?2bbffff 15d0000?15dffff sa350 101011110 128/64 2bc0000?2dfffff 15e0000?15effff sa351 101011111 128/64 2be0000?2bfffff 15f0000?15fffff sa352 101100000 128/64 2c00000?2c1ffff 1600000?160ffff sa353 101100001 128/64 2c20000?2c3ffff 1610000?161ffff sa354 101100010 128/64 2c40000?2c5ffff 1620000?162ffff sa355 101100011 128/64 2c60000?2c7ffff 1630000?163ffff sa356 101100100 128/64 2c80000?2c9ffff 1640000?164ffff sa357 101100101 128/64 2ca0000?2cbffff 1650000?165ffff sa358 101100110 128/64 2cc0000?2cdffff 1660000?166ffff sa359 101100111 128/64 2ce0000?2cfffff 1670000?167ffff sa360 101101000 128/64 2d00000?2d1ffff 1680000?168ffff sa361 101101001 128/64 2d20000?2d3ffff 1690000?169ffff sa362 101101010 128/64 2d40000?2d5ffff 16a0000?16affff sa363 101101011 128/64 2d60000?2d7ffff 16b0000?16bffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 29 advance information sa364 101101100 128/64 2d80000?2d9ffff 16c0000?16cffff sa365 101101101 128/64 2da0000?2dbffff 16d0000?16dffff sa366 101101110 128/64 2dc0000?2ddffff 16e0000?16effff sa367 101101111 128/64 2de0000?2dfffff 16f0000?16fffff sa368 101110000 128/64 2e00000?2e1ffff 1700000?170ffff sa369 101110001 128/64 2e20000?2e3ffff 1710000?171ffff sa370 101110010 128/64 2e40000?2e5ffff 1720000?172ffff sa371 101110011 128/64 2e60000?2e7ffff 1730000?173ffff sa372 101110100 128/64 2e80000?2e9ffff 1740000?174ffff sa373 101110101 128/64 2ea0000?2ebffff 1750000?175ffff sa374 101110110 128/64 2ec0000?2edffff 1760000?176ffff sa375 101110111 128/64 2ee0000?2efffff 1770000?177ffff sa376 101111000 128/64 2f00000?2f1ffff 1780000?178ffff sa377 101111001 128/64 2f20000?2f3ffff 1790000?179ffff sa378 101111010 128/64 2f40000?2f5ffff 17a0000?17affff sa379 101111011 128/64 2f60000?2f7ffff 17b0000?17bffff sa380 101111100 128/64 2f80000?2f9ffff 17c0000?17cffff sa381 101111101 128/64 2fa0000?2fbffff 17d0000?17dffff sa382 101111110 128/64 2fc0000?2fdffff 17e0000?17effff sa383 101111111 128/64 3fe0000?3ffffff 17f0000?17fffff sa384 110000000 128/64 3000000?301ffff 1800000?180ffff sa385 110000001 128/64 3020000?303ffff 1810000?181ffff sa386 110000010 128/64 3040000?305ffff 1820000?182ffff sa387 110000011 128/64 3060000?307ffff 1830000?183ffff sa388 110000100 128/64 3080000?309ffff 1840000?184ffff sa389 110000101 128/64 30a0000?30bffff 1850000?185ffff sa390 110000110 128/64 30c0000?30dffff 1860000?186ffff sa391 110000111 128/64 30e0000?30fffff 1870000?187ffff sa392 110001000 128/64 3100000?311ffff 1880000?188ffff sa393 110001001 128/64 3120000?313ffff 1890000?189ffff sa394 110001010 128/64 3140000?315ffff 18a0000?18affff sa395 110001011 128/64 3160000?317ffff 18b0000?18bffff sa396 110001100 128/64 3180000?319ffff 18c0000?18cffff sa397 110001101 128/64 31a0000?31bffff 18d0000?18dffff sa398 110001110 128/64 31c0000?31dffff 18e0000?18effff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
30 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa399 110001111 128/64 31e0000?31fffff 18f0000?18fffff sa400 110010000 128/64 3200000?321ffff 1900000?190ffff sa401 110010001 128/64 3220000?323ffff 1910000?191ffff sa402 110010010 128/64 3240000?325ffff 1920000?192ffff sa403 110010011 128/64 3260000?327ffff 1930000?193ffff sa404 110010100 128/64 3280000?329ffff 1940000?194ffff sa405 110010101 128/64 32a0000?32bffff 1950000?195ffff sa406 110010110 128/64 32c0000?32dffff 1960000?196ffff sa407 110010111 128/64 32e0000?32fffff 1970000?197ffff sa408 110011000 128/64 3300000?331ffff 1980000?198ffff sa409 110011001 128/64 3320000?333ffff 1990000?199ffff sa410 110011010 128/64 3340000?335ffff 19a0000?19affff sa411 110011011 128/64 3360000?337ffff 19b0000?19bffff sa412 110011100 128/64 3380000?339ffff 19c0000?19cffff sa413 110011101 128/64 33a0000?33bffff 19d0000?19dffff sa414 110011110 128/64 33c0000?33dffff 19e0000?19effff sa415 110011111 128/64 33e0000?33fffff 19f0000?19fffff sa416 110100000 128/64 3400000?341ffff 1a00000?1a0ffff sa417 110100001 128/64 3420000?343ffff 1a10000?1a1ffff sa418 110100010 128/64 3440000?345ffff 1a20000?1a2ffff sa419 110100011 128/64 3460000?347ffff 1a30000?1a3ffff sa420 110100100 128/64 3480000?349ffff 1a40000?1a4ffff sa421 110100101 128/64 34a0000?34bffff 1a50000?1a5ffff sa422 110100110 128/64 34c0000?34dffff 1a60000?1a6ffff sa423 110100111 128/64 34e0000?34fffff 1a70000?1a7ffff sa424 110101000 128/64 3500000?351ffff 1a80000?1a8ffff sa425 110101001 128/64 3520000?353ffff 1a90000?1a9ffff sa426 110101010 128/64 3540000?355ffff 1aa0000?1aaffff sa427 110101011 128/64 3560000?357ffff 1ab0000?1abffff sa428 110101100 128/64 3580000?359ffff 1ac0000?1acffff sa429 110101101 128/64 35a0000?35bffff 1ad0000?1adffff sa430 110101110 128/64 35c0000?35dffff 1ae0000?1aeffff sa431 110101111 128/64 35e0000?35fffff 1af0000?1afffff sa432 110110000 128/64 3600000?361ffff 1b00000?1b0ffff sa433 110110001 128/64 3620000?363ffff 1b10000?1b1ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 31 advance information sa434 110110010 128/64 3640000?365ffff 1b20000?1b2ffff sa435 110110011 128/64 3660000?367ffff 1b30000?1b3ffff sa436 110110100 128/64 3680000?369ffff 1b40000?1b4ffff sa437 110110101 128/64 36a0000?36bffff 1b50000?1b5ffff sa438 110110110 128/64 36c0000?36dffff 1b60000?1b6ffff sa439 110110111 128/64 36e0000?36fffff 1b70000?1b7ffff sa440 110111000 128/64 3700000?371ffff 1b80000?1b8ffff sa441 110111001 128/64 3720000?373ffff 1b90000?1b9ffff sa442 110111010 128/64 3740000?375ffff 1ba0000?1baffff sa443 110111011 128/64 3760000?377ffff 1bb0000?1bbffff sa444 110111100 128/64 3780000?379ffff 1bc0000?1bcffff sa445 110111101 128/64 37a0000?37bffff 1bd0000?1bdffff sa446 110111110 128/64 37c0000?37dffff 1be0000?1beffff sa447 110111111 128/64 37e0000?37fffff 1bf0000?1bfffff sa448 111000000 128/64 3800000?381ffff 1c00000?1c0ffff sa449 111000001 128/64 3820000?383ffff 1c10000?1c1ffff sa450 111000010 128/64 3840000?385ffff 1c20000?1c2ffff sa451 111000011 128/64 3860000?387ffff 1c30000?1c3ffff sa452 111000100 128/64 3880000?389ffff 1c40000?1c4ffff sa453 111000101 128/64 38a0000?38bffff 1c50000?1c5ffff sa454 111000110 128/64 38c0000?38dffff 1c60000?1c6ffff sa455 111000111 128/64 38e0000?38fffff 1c70000?1c7ffff sa456 111001000 128/64 3900000?391ffff 1c80000?1c8ffff sa457 111001001 128/64 3920000?393ffff 1c90000?1c9ffff sa458 111001010 128/64 3940000?395ffff 1ca0000?1caffff sa459 111001011 128/64 3960000?397ffff 1cb0000?1cbffff sa460 111001100 128/64 3980000?399ffff 1cc0000?1ccffff sa461 111001101 128/64 39a0000?39bffff 1cd0000?1cdffff sa462 111001110 128/64 39c0000?39dffff 1ce0000?1ceffff sa463 111001111 128/64 39e0000?39fffff 1cf0000?1cfffff sa464 111010000 128/64 3a00000?3a1ffff 1d00000?1d0ffff sa465 111010001 128/64 3a20000?3a3ffff 1d10000?1d1ffff sa466 111010010 128/64 3a40000?3a5ffff 1d20000?1d2ffff sa467 111010011 128/64 3a60000?3a7ffff 1d30000?1d3ffff sa468 111010100 128/64 3a80000?3a9ffff 1d40000?1d4ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
32 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa469 111010101 128/64 3aa0000?3abffff 1d50000?1d5ffff sa470 111010110 128/64 3ac0000?3adffff 1d60000?1d6ffff sa471 111010111 128/64 3ae0000?3afffff 1d70000?1d7ffff sa472 111011000 128/64 3b00000?3b1ffff 1d80000?1d8ffff sa473 111011001 128/64 3b20000?3b3ffff 1d90000?1d9ffff sa474 111011010 128/64 3b40000?3b5ffff 1da0000?1daffff sa475 111011011 128/64 3b60000?3b7ffff 1db0000?1dbffff sa476 111011100 128/64 3b80000?3b9ffff 1dc0000?1dcffff sa477 111011101 128/64 3ba0000?3bbffff 1dd0000?1ddffff sa478 111011110 128/64 3bc0000?3bdffff 1de0000?1deffff sa479 111011111 128/64 3be0000?3bfffff 1df0000?1dfffff sa480 111100000 128/64 3c00000?3c1ffff 1e00000?1e0ffff sa481 111100001 128/64 3c20000?3c3ffff 1e10000?1e1ffff sa482 111100010 128/64 3c40000?3c5ffff 1e20000?1e2ffff sa483 111100011 128/64 3c60000?3c7ffff 1e30000?1e3ffff sa484 111100100 128/64 3c80000?3c9ffff 1e40000?1e4ffff sa485 111100101 128/64 3ca0000?3cbffff 1e50000?1e5ffff sa486 111100110 128/64 3cc0000?3cdffff 1e60000?1e6ffff sa487 111100111 128/64 3ce0000?3cfffff 1e70000?1e7ffff sa488 111101000 128/64 3d00000?3d1fffff 1e80000?1e8ffff sa489 111101001 128/64 3d20000?3d3ffff 1e90000?1e9ffff sa490 111101010 128/64 3d40000?3d5ffff 1ea0000?1eaffff sa491 111101011 128/64 3d60000?3d7ffff 1eb0000?1ebffff sa492 111101100 128/64 3d80000?3d9ffff 1ec0000?1ecffff sa493 111101101 128/64 3da0000?3dbffff 1ed0000?1edffff sa494 111101110 128/64 3dc0000?3ddffff 1ee0000?1eeffff sa495 111101111 128/64 3de0000?3dfffff 1ef0000?1efffff sa496 111110000 128/64 3e00000?3e1ffff 1f00000?1f0ffff sa497 111110001 128/64 3e20000?3e3ffff 1f10000?1f1ffff sa498 111110010 128/64 3e40000?3e5ffff 1f20000?1f2ffff sa499 111110011 128/64 3e60000?3e7ffff 1f30000?1f3ffff sa500 111110100 128/64 3e80000?3e9ffff 1f40000?1f4ffff sa501 111110101 128/64 3ea0000?3ebffff 1f50000?1f5ffff sa502 111110110 128/64 3ec00000?3edffff 1f60000?1f6ffff sa503 111110111 128/64 3ee0000?3efffff 1f70000?1f7ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 33 advance information sa504 111111000 128/64 3f00000?3f1ffff 1f80000?1f8ffff sa505 111111001 128/64 3f20000?3f3ffff 1f90000?1f9ffff sa506 111111010 128/64 3f40000?3f5ffff 1fa0000?1faffff sa507 111111011 128/64 3f60000?3f7ffff 1fb0000?1fbffff sa508 111111100 128/64 3f80000?3f9ffff 1fc0000?1fcffff sa509 111111101 128/64 3fa0000?3fbffff 1fd0000?1fdffff sa510 111111110 128/64 3fc0000?3fdffff 1fe0000?1feffff sa511 111111111 128/64 3fe0000?3ffffff 1ff0000?1ffffff table 3. sector address table?s29gl256n sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 00000000 128/64 0000000?001ffff 0000000?000ffff sa1 00000001 128/64 0020000?003ffff 0010000?001ffff sa2 00000010 128/64 0040000?005ffff 0020000?002ffff sa3 00000011 128/64 0060000?007ffff 0030000?003ffff sa4 00000100 128/64 0080000?009ffff 0040000?004ffff sa5 00000101 128/64 00a0000?00bffff 0050000?005ffff sa6 00000110 128/64 00c0000?00dffff 0060000?006ffff sa7 00000111 128/64 00e0000?00fffff 0070000?007ffff sa8 00001000 128/64 0100000?011ffff 0080000?008ffff sa9 00001001 128/64 0120000?013ffff 0090000?009ffff sa10 00001010 128/64 0140000?015ffff 00a0000?00affff sa11 00001011 128/64 0160000?017ffff 00b0000?00bffff sa12 00001100 128/64 0180000?019ffff 00c0000?00cffff sa13 00001101 128/64 01a0000?01bffff 00d0000?00dffff sa14 00001110 128/64 01c0000?01dffff 00e0000?00effff sa15 00001111 128/64 01e0000?01fffff 00f0000?00fffff sa16 00010000 128/64 0200000?021ffff 0100000?010ffff sa17 00010001 128/64 0220000?023ffff 0110000?011ffff sa18 00010010 128/64 0240000?025ffff 0120000?012ffff sa19 00010011 128/64 0260000?027ffff 0130000?013ffff sa20 00010100 128/64 0280000?029ffff 0140000?014ffff sa21 00010101 128/64 02a0000?02bffff 0150000?015ffff table 2. sector address table?S29GL512N (continued) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
34 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa22 00010110 128/64 02c0000?02dffff 0160000?016ffff sa23 00010111 128/64 02e0000?02fffff 0170000?017ffff sa24 00011000 128/64 0300000?031ffff 0180000?018ffff sa25 00011001 128/64 0320000?033ffff 0190000?019ffff sa26 00011010 128/64 0340000?035ffff 01a0000?01affff sa27 00011011 128/64 0360000?037ffff 01b0000?01bffff sa28 00011100 128/64 0380000?039ffff 01c0000?01cffff sa29 00011101 128/64 03a0000?03bffff 01d0000?01dffff sa30 00011110 128/64 03c0000?03dffff 01e0000?01effff sa31 00011111 128/64 03e0000?03fffff 01f0000?01fffff sa32 00100000 128/64 0400000?041ffff 0200000?020ffff sa33 00100001 128/64 0420000?043ffff 0210000?021ffff sa34 00100010 128/64 0440000?045ffff 0220000?022ffff sa35 00100011 128/64 0460000?047ffff 0230000?023ffff sa36 00100100 128/64 0480000?049ffff 0240000?024ffff sa37 00100101 128/64 04a0000?04bffff 0250000?025ffff sa38 00100110 128/64 04c0000?04dffff 0260000?026ffff sa39 00100111 128/64 04e0000?04fffff 0270000?027ffff sa40 00101000 128/64 0500000?051ffff 0280000?028ffff sa41 00101001 128/64 0520000?053ffff 0290000?029ffff sa42 00101010 128/64 0540000?055ffff 02a0000?02affff sa43 00101011 128/64 0560000?057ffff 02b0000?02bffff sa44 00101100 128/64 0580000?059ffff 02c0000?02cffff sa45 00101101 128/64 05a0000?05bffff 02d0000?02dffff sa46 00101110 128/64 05c0000?05dffff 02e0000?02effff sa47 00101111 128/64 05e0000?05fffff 02f0000?02fffff sa48 00110000 128/64 0600000?061ffff 0300000?030ffff sa49 00110001 128/64 0620000?063ffff 0310000?031ffff sa50 00110010 128/64 0640000?065ffff 0320000?032ffff sa51 00110011 128/64 0660000?067ffff 0330000?033ffff sa52 00110100 128/64 0680000?069ffff 0340000?034ffff sa53 00110101 128/64 06a0000?06bffff 0350000?035ffff sa54 00110110 128/64 06c0000?06dffff 0360000?036ffff sa55 00110111 128/64 06e0000?06fffff 0370000?037ffff sa56 00111000 128/64 0700000?071ffff 0380000?038ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 35 advance information sa57 00111001 128/64 0720000?073ffff 0390000?039ffff sa58 00111010 128/64 0740000?075ffff 03a0000?03affff sa59 00111011 128/64 0760000?077ffff 03b0000?03bffff sa60 00111100 128/64 0780000?079ffff 03c0000?03cffff sa61 00111101 128/64 07a0000?7bffff 03d0000?03dffff sa62 00111110 128/64 07c0000?07dffff 03e0000?03effff sa63 00111111 128/64 07e0000?07fffff0 03f0000?03fffff sa64 01000000 128/64 0800000?081ffff 0400000?040ffff sa65 01000001 128/64 0820000?083ffff 0410000?041ffff sa66 01000010 128/64 0840000?085ffff 0420000?042ffff sa67 01000011 128/64 0860000?087ffff 0430000?043ffff sa68 01000100 128/64 0880000?089ffff 0440000?044ffff sa69 01000101 128/64 08a0000?08bffff 0450000?045ffff sa70 01000110 128/64 08c0000?08dffff 0460000?046ffff sa71 01000111 128/64 08e0000?08fffff 0470000?047ffff sa72 01001000 128/64 0900000?091ffff 0480000?048ffff sa73 01001001 128/64 0920000?093ffff 0490000?049ffff sa74 01001010 128/64 0940000?095ffff 04a0000?04affff sa75 01001011 128/64 0960000?097ffff 04b0000?04bffff sa76 01001100 128/64 0980000?099ffff 04c0000?04cffff sa77 01001101 128/64 09a0000?09bffff 04d0000?04dffff sa78 01001110 128/64 09c0000?09dffff 04e0000?04effff sa79 01001111 128/64 09e0000?09fffff 04f0000?04fffff sa80 01010000 128/64 0a00000?0a1ffff 0500000?050ffff sa81 01010001 128/64 0a20000?0a3ffff 0510000?051ffff sa82 01010010 128/64 0a40000?045ffff 0520000?052ffff sa83 01010011 128/64 0a60000?0a7ffff 0530000?053ffff sa84 01010100 128/64 0a80000?0a9ffff 0540000?054ffff sa85 01010101 128/64 0aa0000?0abffff 0550000?055ffff sa86 01010110 128/64 0ac0000?0adffff 0560000?056ffff sa87 01010111 128/64 0ae0000?aefffff 0570000?057ffff sa88 01011000 128/64 0b00000?0b1ffff 0580000?058ffff sa89 01011001 128/64 0b20000?0b3ffff 0590000?059ffff sa90 01011010 128/64 0b40000?0b5ffff 05a0000?05affff sa91 01011011 128/64 0b60000?0b7ffff 05b0000?05bffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
36 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa92 01011100 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 01011101 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 01011110 128/64 0bc0000?0bdffff 05e0000?05effff sa95 01011111 128/64 0be0000?0bfffff 05f0000?05fffff sa96 01100000 128/64 0c00000?0c1ffff 0600000?060ffff sa97 01100001 128/64 0c20000?0c3ffff 0610000?061ffff sa98 01100010 128/64 0c40000?0c5ffff 0620000?062ffff sa99 01100011 128/64 0c60000?0c7ffff 0630000?063ffff sa100 01100100 128/64 0c80000?0c9ffff 0640000?064ffff sa101 01100101 128/64 0ca0000?0cbffff 0650000?065ffff sa102 01100110 128/64 0cc0000?0cdffff 0660000?066ffff sa103 01100111 128/64 0ce0000?0cfffff 0670000?067ffff sa104 01101000 128/64 0d00000?0d1ffff 0680000?068ffff sa105 01101001 128/64 0d20000?0d3ffff 0690000?069ffff sa106 01101010 128/64 0d40000?0d5ffff 06a0000?06affff sa107 01101011 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 01101100 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 01101101 128/64 0da0000?0dbffff 06d0000?06dffff sa110 01101110 128/64 0dc0000?0ddffff 06e0000?06effff sa111 01101111 128/64 0de0000?0dfffff 06f0000?06fffff sa112 01110000 128/64 0e00000?0e1ffff 0700000?070ffff sa113 01110001 128/64 0e20000?0e3ffff 0710000?071ffff sa114 01110010 128/64 0e40000?0e5ffff 0720000?072ffff sa115 01110011 128/64 0e60000?0e7ffff 0730000?073ffff sa116 01110100 128/64 0e80000?0e9ffff 0740000?074ffff sa117 01110101 128/64 0ea0000?0ebffff 0750000?075ffff sa118 01110110 128/64 0ec0000?0edffff 0760000?076ffff sa119 01110111 128/64 0ee0000?0efffff 0770000?077ffff sa120 01111000 128/64 0f00000?0f1ffff 0780000?078ffff sa121 01111001 128/64 0f20000?0f3ffff 0790000?079ffff sa122 01111010 128/64 0f40000?0f5ffff 07a0000?07affff sa123 01111011 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 01111100 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 01111101 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 01111110 128/64 0fc0000?0fdffff 07e0000?07effff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 37 advance information sa127 01111111 128/64 0fe0000?0ffffff 07f0000?07fffff sa128 10000000 128/64 1000000?101ffff 0800000?080ffff sa129 10000001 128/64 1020000?103ffff 0810000?081ffff sa130 10000010 128/64 1040000?105ffff 0820000?082ffff sa131 10000011 128/64 1060000?107ffff 0830000?083ffff sa132 10000100 128/64 1080000?109ffff 0840000?084ffff sa133 10000101 128/64 10a0000?10bffff 0850000?085ffff sa134 10000110 128/64 10c0000?10dffff 0860000?086ffff sa135 10000111 128/64 10e0000?10fffff 0870000?087ffff sa136 10001000 128/64 1100000?111ffff 0880000?088ffff sa137 10001001 128/64 1120000?113ffff 0890000?089ffff sa138 10001010 128/64 1140000?115ffff 08a0000?08affff sa139 10001011 128/64 1160000?117ffff 08b0000?08bffff sa140 10001100 128/64 1180000?119ffff 08c0000?08cffff sa141 10001101 128/64 11a0000?11bffff 08d0000?08dffff sa142 10001110 128/64 11c0000?11dffff 08e0000?08effff sa143 10001111 128/64 11e0000?11fffff 08f0000?08fffff sa144 10010000 128/64 1200000?121ffff 0900000?090ffff sa145 10010001 128/64 1220000?123ffff 0910000?091ffff sa146 10010010 128/64 1240000?125ffff 0920000?092ffff sa147 10010011 128/64 1260000?127ffff 0930000?093ffff sa148 10010100 128/64 1280000?129ffff 0940000?094ffff sa149 10010101 128/64 12a0000?12bffff 0950000?095ffff sa150 10010110 128/64 12c0000?12dffff 0960000?096ffff sa151 10010111 128/64 12e0000?12fffff 0970000?097ffff sa152 10011000 128/64 1300000?131ffff 0980000?098ffff sa153 10011001 128/64 1320000?133ffff 0990000?099ffff sa154 10011010 128/64 1340000?135ffff 09a0000?09affff sa155 10011011 128/64 1360000?137ffff 09b0000?09bffff sa156 10011100 128/64 1380000?139ffff 09c0000?09cffff sa157 10011101 128/64 13a0000?13bffff 09d0000?09dffff sa158 10011110 128/64 13c0000?13dffff 09e0000?09effff sa159 10011111 128/64 13e0000?13fffff 09f0000?09fffff sa160 10100000 128/64 1400000?141ffff 0a00000?0a0ffff sa161 10100001 128/64 1420000?143ffff 0a10000?0a1ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
38 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa162 10100010 128/64 1440000?145ffff 0a20000?0a2ffff sa163 10100011 128/64 1460000?147ffff 0a30000?0a3ffff sa164 10100100 128/64 1480000?149ffff 0a40000?0a4ffff sa165 10100101 128/64 14a0000?14bffff 0a50000?0a5ffff sa166 10100110 128/64 14c0000?14dffff 0a60000?0a6ffff sa167 10100111 128/64 14e0000?14fffff 0a70000?0a7ffff sa168 10101000 128/64 1500000?151ffff 0a80000?0a8ffff sa169 10101001 128/64 1520000?153ffff 0a90000?0a9ffff sa170 10101010 128/64 1540000?155ffff 0aa0000?0aaffff sa171 10101011 128/64 1560000?157ffff 0ab0000?0abffff sa172 10101100 128/64 1580000?159ffff 0ac0000?0acffff sa173 10101101 128/64 15a0000?15bffff 0ad0000?0adffff sa174 10101110 128/64 15c0000?15dffff 0ae0000?0aeffff sa175 10101111 128/64 15e0000?15fffff 0af0000?0afffff sa176 10110000 128/64 1600000?161ffff 0b00000?0b0ffff sa177 10110001 128/64 1620000?163ffff 0b10000?0b1ffff sa178 10110010 128/64 1640000?165fffff 0b20000?0b2ffff sa179 10110011 128/64 1660000?167ffff 0b30000?0b3ffff sa180 10110100 128/64 1680000?169ffff 0b40000?0b4ffff sa181 10110101 128/64 16a0000?16bffff 0b50000?0b5ffff sa182 10110110 128/64 16c0000?16dffff 0b60000?0b6ffff sa183 10110111 128/64 16e0000?16fffff 0b70000?0b7ffff sa184 10111000 128/64 1700000?171ffff 0b80000?0b8ffff sa185 10111001 128/64 1720000?173ffff 0b90000?0b9ffff sa186 10111010 128/64 1740000?175ffff 0ba0000?0baffff sa187 10111011 128/64 1760000?177ffff 0bb0000?0bbffff sa188 10111100 128/64 1780000?179ffff 0bc0000?0bcffff sa189 10111101 128/64 17a0000?17bffff 0bd0000?0bdffff sa190 10111110 128/64 17c0000?17dffff 0be0000?0beffff sa191 10111111 128/64 17e0000?17fffff 0bf0000?0bfffff sa192 11000000 128/64 1800000?181ffff 0c00000?0c0ffff sa193 11000001 128/64 1820000?183ffff 0c10000?0c1ffff sa194 11000010 128/64 1840000?185ffff 0c20000?0c2ffff sa195 11000011 128/64 1860000?187ffff 0c30000?0c3ffff sa196 11000100 128/64 1880000?189ffff 0c40000?0c4ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 39 advance information sa197 11000101 128/64 18a0000?18bffff 0c50000?0c5ffff sa198 11000110 128/64 18c0000?18dffff 0c60000?0c6ffff sa199 11000111 128/64 18e0000?18fffff 0c70000?0c7ffff sa200 11001000 128/64 1900000?191ffff 0c80000?0c8ffff sa201 11001001 128/64 1920000?193ffff 0c90000?0c9ffff sa202 11001010 128/64 1940000?195ffff 0ca0000?0caffff sa203 11001011 128/64 1960000?197ffff 0cb0000?0cbffff sa204 11001100 128/64 1980000?199ffff 0cc0000?0ccffff sa205 11001101 128/64 19a0000?19bffff 0cd0000?0cdffff sa206 11001110 128/64 19c0000?19dffff 0ce0000?0ceffff sa207 11001111 128/64 19e0000?19ffff 0cf0000?0cfffff sa208 11010000 128/64 1a00000?1a1ffff 0d00000?0d0ffff sa209 11010001 128/64 1a20000?1a3ffff 0d10000?0d1ffff sa210 11010010 128/64 1a40000?1a5ffff 0d20000?0d2ffff sa211 11010011 128/64 1a60000?1a7ffff 0d30000?0d3ffff sa212 11010100 128/64 1a80000?1a9ffff 0d40000?0d4ffff sa213 11010101 128/64 1aa0000?1abffff 0d50000?0d5ffff sa214 11010110 128/64 1ac0000?1adffff 0d60000?0d6ffff sa215 11010111 128/64 1ae0000?1afffff 0d70000?0d7ffff sa216 11011000 128/64 1b00000?1b1ffff 0d80000?0d8ffff sa217 11011001 128/64 1b20000?1b3ffff 0d90000?0d9ffff sa218 11011010 128/64 1b40000?1b5ffff 0da0000?0daffff sa219 11011011 128/64 1b60000?1b7ffff 0db0000?0dbffff sa220 11011100 128/64 1b80000?1b9ffff 0dc0000?0dcffff sa221 11011101 128/64 1ba0000?1bbffff 0dd0000?0ddffff sa222 11011110 128/64 1bc0000?1bdffff 0de0000?0deffff sa223 11011111 128/64 1be0000?1bfffff 0df0000?0dfffff sa224 11100000 128/64 1c00000?1c1ffff 0e00000?0e0ffff sa225 11100001 128/64 1c20000?1c3ffff 0e10000?0e1ffff sa226 11100010 128/64 1c40000?1c5ffff 0e20000?0e2ffff sa227 11100011 128/64 1c60000?1c7ffff 0e30000?0e3ffff sa228 11100100 128/64 1c80000?1c9ffff 0e40000?0e4ffff sa229 11100101 128/64 1ca0000?1cbffff 0e50000?0e5ffff sa230 11100110 128/64 1cc0000?1cdffff 0e60000?0e6ffff sa231 11100111 128/64 1ce0000?1cfffff 0e70000?0e7ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
40 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa232 11101000 128/64 1d00000?1d1ffff 0e80000?0e8ffff sa233 11101001 128/64 1d20000?1d3ffff 0e90000?0e9ffff sa234 11101010 128/64 1d40000?1d5ffff 0ea0000?0eaffff sa235 11101011 128/64 1d60000?1d7ffff 0eb0000?0ebffff sa236 11101100 128/64 1d80000?1d9ffff 0ec0000?0ecffff sa237 11101101 128/64 1da0000?1dbffff 0ed0000?0edffff sa238 11101110 128/64 1dc0000?1ddffff 0ee0000?0eeffff sa239 11101111 128/64 1de0000?1dfffff 0ef0000?0efffff sa240 11110000 128/64 1e00000?1e1ffff 0f00000?0f0ffff sa241 11110001 128/64 1e20000?1e3ffff 0f10000?0f1ffff sa242 11110010 128/64 1e40000?1e5ffff 0f20000?0f2ffff sa243 11110011 128/64 1e60000?137ffff 0f30000?0f3ffff sa244 11110100 128/64 1e80000?1e9ffff 0f40000?0f4ffff sa245 11110101 128/64 1ea0000?1ebffff 0f50000?0f5ffff sa246 11110110 128/64 1ec0000?1edffff 0f60000?0f6ffff sa247 11110111 128/64 1ee0000?1efffff 0f70000?0f7ffff sa248 11111000 128/64 1f00000?1f1ffff 0f80000?0f8ffff sa249 11111001 128/64 1f20000?1f3ffff 0f90000?0f9ffff sa250 11111010 128/64 1f40000?1f5ffff 0fa0000?0faffff sa251 11111011 128/64 1f60000?1f7ffff 0fb0000?0fbffff sa252 11111100 128/64 1f80000?1f9ffff 0fc0000?0fcffff sa253 11111101 128/64 1fa0000?1fbffff 0fd0000?0fdffff sa254 11111110 128/64 1fc0000?1fdffff 0fe0000?0feffff sa255 11111111 128/64 1fe0000?1ffffff 0ff0000?0ffffff table 4. sector address table?s29gl128n sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 128/64 0000000?001ffff 0000000?000ffff sa1 0 0 0 0 0 1 128/64 0020000?003ffff 0010000?001ffff sa2 0 0 0 0 1 0 128/64 0040000?005ffff 0020000?002ffff sa3 0 0 0 0 1 1 128/64 0060000?007ffff 0030000?003ffff sa4 0 0 0 1 0 0 128/64 0080000?009ffff 0040000?004ffff sa5 0 0 0 1 0 1 128/64 00a0000?00bffff 0050000?005ffff table 3. sector address table?s29gl256n (continued) sector a23?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 41 advance information sa6 0 0 0 1 1 0 128/64 00c0000?00dffff 0060000?006ffff sa7 0 0 0 1 1 1 128/64 00e0000?00fffff 0070000?007ffff sa8 0 0 1 0 0 0 128/64 0100000?011ffff 0080000?008ffff sa9 0 0 1 0 0 1 128/64 0120000?013ffff 0090000?009ffff sa10 0 0 1 0 1 0 128/64 0140000?015ffff 00a0000?00affff sa11 0 0 1 0 1 1 128/64 0160000?017ffff 00b0000?00bffff sa12 0 0 1 1 0 0 128/64 0180000?019ffff 00c0000?00cffff sa13 0 0 1 1 0 1 128/64 01a0000?01bffff 00d0000?00dffff sa14 0 0 1 1 1 0 128/64 01c0000?01dffff 00e0000?00effff sa15 0 0 1 1 1 1 128/64 01e0000?01fffff 00f0000?00fffff sa16 0 1 0 0 0 0 128/64 0200000?021ffff 0100000?010ffff sa17 0 1 0 0 0 1 128/64 0220000?023ffff 0110000?011ffff sa18 0 1 0 0 1 0 128/64 0240000?025ffff 0120000?012ffff sa19 0 1 0 0 1 1 128/64 0260000?027ffff 0130000?013ffff sa20 0 1 0 1 0 0 128/64 0280000?029ffff 0140000?014ffff sa21 0 1 0 1 0 1 128/64 02a0000?02bffff 0150000?015ffff sa22 0 1 0 1 1 0 128/64 02c0000?02dffff 0160000?016ffff sa23 0 1 0 1 1 1 128/64 02e0000?02fffff 0170000?017ffff sa24 0 1 1 0 0 0 128/64 0300000?031ffff 0180000?018ffff sa25 0 1 1 0 0 1 128/64 0320000?033ffff 0190000?019ffff sa26 0 1 1 0 1 0 128/64 0340000?035ffff 01a0000?01affff sa27 0 1 1 0 1 1 128/64 0360000?037ffff 01b0000?01bffff sa28 0 1 1 1 0 0 128/64 0380000?039ffff 01c0000?01cffff sa29 0 1 1 1 0 1 128/64 03a0000?03bffff 01d0000?01dffff sa30 0 1 1 1 1 0 128/64 03c0000?03dffff 01e0000?01effff sa31 0 1 1 1 1 1 128/64 03e0000?03fffff 01f0000?01fffff sa32 1 0 0 0 0 0 128/64 0400000?041ffff 0200000?020ffff sa33 1 0 0 0 0 1 128/64 0420000?043ffff 0210000?021ffff sa34 1 0 0 0 1 0 128/64 0440000?045ffff 0220000?022ffff sa35 1 0 0 0 1 1 128/64 0460000?047ffff 0230000?023ffff sa36 1 0 0 1 0 0 128/64 0480000?049ffff 0240000?024ffff sa37 1 0 0 1 0 1 128/64 04a0000?04bffff 0250000?025ffff sa38 1 0 0 1 1 0 128/64 04c0000?04dffff 0260000?026ffff sa39 1 0 0 1 1 1 128/64 04e0000?04fffff 0270000?027ffff sa40 1 0 1 0 0 0 128/64 0500000?051ffff 0280000?028ffff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
42 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information sa41 1 0 1 0 0 1 128/64 0520000?053ffff 0290000?029ffff sa42 1 0 1 0 1 0 128/64 0540000?055ffff 02a0000?02affff sa43 1 0 1 0 1 1 128/64 0560000?057ffff 02b0000?02bffff sa44 1 0 1 1 0 0 128/64 0580000?059ffff 02c0000?02cffff sa45 1 0 1 1 0 1 128/64 05a0000?05bffff 02d0000?02dffff sa46 1 0 1 1 1 0 128/64 05c0000?05dffff 02e0000?02effff sa47 1 0 1 1 1 1 128/64 05e0000?05fffff 02f0000?02fffff sa48 1 1 0 0 0 0 128/64 0600000?061ffff 0300000?030ffff sa49 1 1 0 0 0 1 128/64 0620000?063ffff 0310000?031ffff sa50 1 1 0 0 1 0 128/64 0640000?065ffff 0320000?032ffff sa51 1 1 0 0 1 1 128/64 0660000?067ffff 0330000?033ffff sa52 1 1 0 1 0 0 128/64 0680000?069ffff 0340000?034ffff sa53 1 1 0 1 0 1 128/64 06a0000?06bffff 0350000?035ffff sa54 1 1 0 1 1 0 128/64 06c0000?06dffff 0360000?036ffff sa55 1 1 0 1 1 1 128/64 06e0000?06fffff 0370000?037ffff sa56 1 1 1 0 0 0 128/64 0700000?071ffff 0380000?038ffff sa57 1 1 1 0 0 1 128/64 0720000?073ffff 0390000?039ffff sa58 1 1 1 0 1 0 128/64 0740000?075ffff 03a0000?03affff sa59 1 1 1 0 1 1 128/64 0760000?077ffff 03b0000?03bffff sa60 1 1 1 1 0 0 128/64 0780000?079ffff 03c0000?03cffff sa61 1 1 1 1 0 1 128/64 07a0000?07bffff 03d0000?03dffff sa62 1 1 1 1 1 0 128/64 07c0000?07dffff 03e0000?03effff sa63 1 1 1 1 1 1 128/64 07e0000?07fffff 03f0000?03fffff sa64 0 0 0 0 0 0 128/64 0800000?081ffff 0400000?040ffff sa65 0 0 0 0 0 1 128/64 0820000?083ffff 0410000?041ffff sa66 0 0 0 0 1 0 128/64 0840000?085ffff 0420000?042ffff sa67 0 0 0 0 1 1 128/64 0860000?087ffff 0430000?043ffff sa68 0 0 0 1 0 0 128/64 0880000?089ffff 0440000?044ffff sa69 0 0 0 1 0 1 128/64 08a0000?08bffff 0450000?045ffff sa70 0 0 0 1 1 0 128/64 08c0000?08dffff 0460000?046ffff sa71 0 0 0 1 1 1 128/64 08e0000?08fffff 0470000?047ffff sa72 0 0 1 0 0 0 128/64 0900000?091ffff 0480000?048ffff sa73 0 0 1 0 0 1 128/64 0920000?093ffff 0490000?049ffff sa74 0 0 1 0 1 0 128/64 0940000?095ffff 04a0000?04affff sa75 0 0 1 0 1 1 128/64 0960000?097ffff 04b0000?04bffff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 43 advance information sa76 0 0 1 1 0 0 128/64 0980000?099ffff 04c0000?04cffff sa77 0 0 1 1 0 1 128/64 09a0000?09bffff 04d0000?04dffff sa78 0 0 1 1 1 0 128/64 09c0000?09dffff 04e0000?04effff sa79 0 0 1 1 1 1 128/64 09e0000?09fffff 04f0000?04fffff sa80 0 1 0 0 0 0 128/64 0a00000?0a1ffff 0500000?050ffff sa81 0 1 0 0 0 1 128/64 0a20000?0a3ffff 0510000?051ffff sa82 0 1 0 0 1 0 128/64 0a40000?0a5ffff 0520000?052ffff sa83 0 1 0 0 1 1 128/64 0a60000?0a7ffff 0530000?053ffff sa84 0 1 0 1 0 0 128/64 0a80000?0a9ffff 0540000?054ffff sa85 0 1 0 1 0 1 128/64 0aa0000?0abffff 0550000?055ffff sa86 0 1 0 1 1 0 128/64 0ac0000?0adffff 0560000?056ffff sa87 0 1 0 1 1 1 128/64 0ae0000?0afffff 0570000?057ffff sa88 0 1 1 0 0 0 128/64 0b00000?0b1ffff 0580000?058ffff sa89 0 1 1 0 0 1 128/64 0b20000?0b3ffff 0590000?059ffff sa90 0 1 1 0 1 0 128/64 0b40000?0b5ffff 05a0000?05affff sa91 0 1 1 0 1 1 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 0 1 1 1 0 0 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 0 1 1 1 0 1 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 0 1 1 1 1 0 128/64 0bc0000?0bdffff 05e0000?05effff sa95 0 1 1 1 1 1 128/64 0be0000?0bfffff 05f0000?05fffff sa96 1 0 0 0 0 0 128/64 0c00000?0c1ffff 0600000?060ffff sa97 1 0 0 0 0 1 128/64 0c20000?0c3ffff 0610000?061ffff sa98 1 0 0 0 1 0 128/64 0c40000?0c5ffff 0620000?062ffff sa99 1 0 0 0 1 1 128/64 0c60000?0c7ffff 0630000?063ffff sa100 1 0 0 1 0 0 128/64 0c80000?0c9ffff 0640000?064ffff sa101 1 0 0 1 0 1 128/64 0ca0000?0cbffff 0650000?065ffff sa102 1 0 0 1 1 0 128/64 0cc0000?0cdffff 0660000?066ffff sa103 1 0 0 1 1 1 128/64 0ce0000?0cfffff 0670000?067ffff sa104 1 0 1 0 0 0 128/64 0d00000?0d1ffff 0680000?068ffff sa105 1 0 1 0 0 1 128/64 0d20000?0d3ffff 0690000?069ffff sa106 1 0 1 0 1 0 128/64 0d40000?0d5ffff 06a0000?06affff sa107 1 0 1 0 1 1 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 1 0 1 1 0 0 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 1 0 1 1 0 1 128/64 0da0000?0dbffff 06d0000?06dffff sa110 1 0 1 1 1 0 128/64 0dc0000?0ddffff 06e0000?06effff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
44 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information autoselect mode the autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its co rresponding programming algorithm. how- ever, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires vid on ad- dress pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in table 5 . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2 ). table 5 shows the re- maining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding iden- tifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in table 12 and table 13 . this method does not require v id . refer to the autoselect command sequence section for more information. sa111 1 0 1 1 1 1 128/64 0de0000?0dfffff 06f0000?06fffff sa112 1 1 0 0 0 0 128/64 0e00000?0e1ffff 0700000?070ffff sa113 1 1 0 0 0 1 128/64 0e20000?0e3ffff 0710000?071ffff sa114 1 1 0 0 1 0 128/64 0e40000?0e5ffff 0720000?072ffff sa115 1 1 0 0 1 1 128/64 0e60000?0e7ffff 0730000?073ffff sa116 1 1 0 1 0 0 128/64 0e80000?0e9ffff 0740000?074ffff sa117 1 1 0 1 0 1 128/64 0ea0000?0ebffff 0750000?075ffff sa118 1 1 0 1 1 0 128/64 0ec0000?0edffff 0760000?076ffff sa119 1 1 0 1 1 1 128/64 0ee0000?0efffff 0770000?077ffff sa120 1 1 1 0 0 0 128/64 0f00000?0f1ffff 0780000?078ffff sa121 1 1 1 0 0 1 128/64 0f20000?0f3ffff 0790000?079ffff sa122 1 1 1 0 1 0 128/64 0f40000?0f5ffff 07a0000?07affff sa123 1 1 1 0 1 1 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 1 1 1 1 0 0 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 1 1 1 1 0 1 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 1 1 1 1 1 0 128/64 0fc0000?0fdffff 07e0000?07effff sa127 1 1 1 1 1 1 128/64 0fe0000?0ffffff 07f0000?07fffff table 4. sector address table?s29gl128n (continued) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 45 advance information ta b l e 5 . autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled pro- tection method. password sector protection a highly sophisticated protection meth od that requires a password before changes to certain sectors or sector groups are permitted wp# hardware protection a write protect pin that can prevent program or erase operations in the outermost sectors. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. selecting a sector protection mode all parts default to operate in the persistent sector protection mode. the cus- tomer must then choose if the persistent or password protection method is most desirable. there are two one-time progra mmable non-volatile bits that define which sector protection method will be used. if the customer decides to continue description ce# oe# we # a22 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte#= v ih byte# = v il manufacturer id : spansion product llhxxv id x l x l l l 00 x 01h device id S29GL512N cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 h h l 22 x 23h cycle 3 h h h 22 x 01h device id s29gl256n cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 h h l 22 x 22h cycle 3 h h h 22 x 01h device id s29gl128n cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 h h l 22 x 21h cycle 3 h h h 22 x 01h sector group protection verification llhsaxv id xl x l h l x x 01h (protected), 00h (unprotected) secsi sector indicator bit (dq7), wp# protects highest address sector llhxxv id xl x l h h x x 98h (factory locked), 18h (not factory locked) secsi sector indicator bit (dq7), wp# protects lowest address sector llhxxv id xl x l h h x x 88h (factory locked), 08h (not factory locked)
46 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information using the persistent sector protection method, they must set the persistent sector protection mode locking bit . this will permanently set the part to op- erate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit . this will permanently set the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protec- tion mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unex- pected shift from the default persistent sector protection mode into the password protection mode. the device is shipped with all sectors unprotected. the factory offers the option of programming and protecting sectors at the factory prior to shipping the device through the expressflash? service. contact your sales representative for details. it is possible to determine whether a sector is protected or unprotected. see ?au- toselect command sequence? section on page 58 for details. advanced sector protection advanced sector protection features several levels of sector protection, which can disable both the program and erase operations in certain sectors. persistent sector protection is a method that replaces the old 12v controlled protection method. password sector protection is a highly sophisticated protection method that requires a password before changes to certain sectors are permitted. advanced sector protection is available when acc = v hh . lock register the lock register consists of 3 bits (dq2, dq1, and dq0). these dq2, dq1, dq0 bits of the lock register are programmable by the user. users are not allowed to program both dq2 and dq1 bits of the lock register to the 00 state. if the user tries to program dq2 and dq1 bits of the lock register to the 00 state, the device will abort the lock register back to the default 11 state. the programming time of the lock register is same as the typical word programming time without uti- lizing the write buffer of the device. during a lock register programming sequence execution, the dq6 toggle bit i will toggle until the programming of the lock register has completed to indicate programming status. all lock register bits are readable to allow users to verify lock register statuses. initial access delay is required to read the lock register. the customer secsi sector protection bit is dq0, persistent protection mode lock bit is dq1, and password protection mode lock bit is dq2 are accessible by all users. each of these bits are non-volatile. dq15-dq3 are reserved and must be 1's when the user tries to program the dq 2, dq1, and dq0 bits of the lock reg- ister. the user is not required to program dq2, dq1 and dq0 bits of the lock register at the same time. this allows users to lock the secsi sector and then set the device either permanently into password protection mode or persistent pro- tection mode and then lock the secsi sector at separate instances and time frames.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 47 advance information ? secsi sector protection allows the user to lock the secsi sector area ? persistent protection mode lock bit allows the user to set the device perma- nently to operate in the persistent protection mode ? password protection mode lock bit allows the user to set the device perma- nently to operate in the password protection mode ta b l e 6 . lock register persistent sector protection the persistent sector protection method replaces the old 12 v controlled protec- tion method while at the same time enhancing flexibility by providing three different sector protection states: ? dynamically locked -the sector is protected and can be changed by a sim- ple command ? persistently locked -a sector is protected and cannot be changed ? unlocked -the sector is unprotected and can be changed by a simple com- mand in order to achieve these states, three types of ?bits? are going to be used: dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dyb bits are in the ?unprotected state? if the dyb lock bit of the ?lock register? is not programmed. if the dyb lock bit of the ?lock register? is programmed, all dyb bits wi ll power-up or hardware reset to the ?protected state?. each dyb is individually modifiable through the dyb set com- mand and dyb clear command. when the parts are first shipped, all of the persistent protect bits (ppb) are cleared into the unprotected state. the dyb bits and ppb lock bit are defaulted to power up in the cleared state or unprotected state - meaning the all ppb bits are changeable. the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppb bits cleared, the dyb bits control whether or not the sector is protected or unprotected. by is- suing the dyb set and dyb clear command sequences, the dyb bits will be protected or unprotected, thus placing each sector in the protected or unpro- tected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth be- tween the protected and un-protected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy re- moval of protection when changes are needed. the dyb bits maybe set or cleared as often as needed. the ppb bits allow for a more static, and difficult to change, level of protection. the ppb bits retain their state across power cycles because they are non-volatile. individual ppb bits are set with a program command but must all be cleared as a group through an erase command. the ppb lock bit adds an additional level of protection. once all ppb bits are pro- grammed to the desired settings, the ppb lock bit may be set to the ?freeze dq15-3 dq2 dq1 dq0 don?t care password protection mode lock bit persistent protection mode lock bit secsi sector protection bit
48 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information state?. setting the ppb lock bit to the ?freeze state? disables all program and erase commands to the non-volatile ppb bits. in effect, the ppb lock bit locks the ppb bits into their current state. the only way to clear the ppb lock bit to the ?unfreeze state? is to go through a power cycle, or hardware reset. the software reset command will not clear the ppb lock bit to the ?unfreeze state?. system boot code can determine if any changes to the ppb bits are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock bit to disable any further changes to the ppb bits during system operation. the wp# write protect pin adds a final level of hardware protection. when this pin is low it is not possible to change the contents of the wp# protected sectors. these sectors generally hold system boot code. so, the wp# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. the dyb set and dyb clear commands for the dynamic sectors switch the dyb bits to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled to the ?unfreeze state? by either putting the device through a power-cycle, or hardware reset. the ppb bits can then be changed to reflect the desired settings. setting the ppb lock bit once again to the ?freeze state? will lock the ppb bits, and the device operates normally again. note: to achieve the best protection, it's recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to each sector. if a ppb is programmed to the protected state through the ?ppb program? command, that sector will be protected from program or erase operations will be read-only. if a ppb requires erasure, all of the sector ppb bits must first be erased in parallel through the ?all ppb erase? command. the ?all ppb erase? command will prepro- grammed all ppb bits prior to ppb erasing. all ppb bits erase in parallel, unlike programming where individual ppb bits are programmable. the ppb bits have the same endurance as the flash memory. programming the ppb bit requires the typical word programming time without uti- lizing the write buffer. during a ppb bit programming and a11 ppb bit erasing sequence execution, the dq6 toggle bit i will toggle until the programming of the ppb bit or erasing of all ppb bits has completed to indicate programming and erasing status. erasing all of the ppb bits at once requires typical sector erase time. during the erasing of all ppb bits, the dq3 sector erase timer bit will output a 1 to indicate the erasure of all ppb bits are in progress. when the erasure of all ppb bits has completed, the dq3 sector erase timer bit will output a 0 to indicate that all ppb bits have been erased. reading the ppb status bit requires the initial access time of the device.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 49 advance information persistent protection bit lock (ppb lock bit) a global volatile bit. when set to the ?freeze state?, the ppb bits cannot be changed. when cleared to the ?unfreeze state?, the ppb bits are changeable. there is only one ppb lock bit per device. the ppb lock bit is cleared to the ?un- freeze state? after power-up or hardware reset. there is no command sequence to unlock or ?unfreeze? the ppb lock bit. configuring the ppb lock bit to the free ze state requires approximately 100ns. reading the ppb lock status bit requires the initial access time of the device. ta b l e 7 . sector protection schemes table 7 contains all possible combinations of the dyb bit, ppb bit, and ppb lock bit relating to the status of the sector. in summary, if the ppb bit is set, and the ppb lock bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the ppb lock bit to ?unfreeze state?. if the ppb bit is cleared, the sector can be dynamically locked or unlocked. the dyb bit then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sec- tor enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. the programming of the dyb bit, ppb bit, and ppb lock bit for a given sec- tor can be verified by writing a dyb status read, ppb status read, and ppb lock status read commands to the device. the autoselect sector protection verification outputs the or function of the dyb bit and ppb bit per sector basis. when the or function of the dyb bit and ppb bit is a 1, the sector is either protected by dyb or ppb or both. when the or function of the dyb bit and ppb bit is a 0, the sector is unprotected through both the dyb and ppb. persistent protection mode lock bit like the password protection mode lock bit, a persistent protection mode lock bit exists to guarantee that the device remain in software sector protection. once programmed, the persistent protection mode lock bit prevents programming of protection states sector state dyb bit ppb bit ppb lock bit unprotect unprotect unfreeze unprotected ? ppb and dyb are changeable unprotect unprotect freeze unprotected ? ppb not changeable, dyb is changeable unprotect protect unfreeze protected ? ppb and dyb are changeable unprotect protect freeze protected ? ppb not changeable, dyb is changeable protect unprotect unfreeze protected ? ppb and dyb are changeable protect unprotect freeze protected ? ppb not changeable, dyb is changeable protect protect unfreeze protected ? ppb and dyb are changeable protect protect freeze protected ? ppb not changeable, dyb is changeable
50 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information the password protection mode lock bit. this guarantees that a hacker could not place the device in password protection mode. the password protection mode lock bit resides in the ?lock register?. password sector protection the password sector protection method allows an even higher level of security than the persistent sector protection method. there are two main differences be- tween the persistent sector protection and the password sector protection methods: ? when the device is first powered on, or comes out of a reset cycle, the ppb lock bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. ? the only means to clear and unfreeze the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region outside of the flash memory. once the password protection mode lock bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear and unfreeze the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally com- pares the given password with the pre-pr ogrammed password. if they match, the ppb lock bit is cleared to the ?unfreezed state?, and the ppb bits can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check? after the valid 64-bit password has been entered for the ppb lock bit to be cleared to the ?unfreezed state?. this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password protection mode lock bit in order to select the password sector protection method, the customer must first program the password. the factory recommends that the password be somehow correlated to the unique electronic serial number (esn) of the particular flash de- vice. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password read operations. once the desired pass- word is programmed in, the customer must then set the password protection mode lock bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password sector protec- tion method is desired when programming the password protection mode lock bit. more importantly, the user must be sure that the password is correct when the password protection mode lock bit is programmed. due to the fact that read operations are disabled, there is no means to read what the password is after- wards. if the password is lost after programming the password protection mode
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 51 advance information lock bit, there will be no way to clear and unfreeze the ppb lock bit. the pass- word protection mode lock bit, once programmed, prevents reading the 64-bit password on the dq bus and further password programming. the password pro- tection mode lock bit is not erasable. once password protection mode lock bit is programmed, the persistent protection mode lock bit is disabled from program- ming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and password read commands. the password function works in conjunction with the password protection mode lock bit, which when programmed, prevents the password read command from reading the con- tents of the password on the pins of the device. persistent protection bit lock (ppb lock bit) a global volatile bit. the ppb lock bit is a volatile bit that reflects the state of the password protection mode lock bit after power-up reset. if the password protec- tion mode lock bit is also programme d after programming the password, the password unlock command must be issued to clear and unfreeze the ppb lock bit after a hardware reset (reset# asserted) or a power-up reset. successful exe- cution of the password unlock command clears and unfreezes the ppb lock bit, allowing for sector ppb bits to be modified. without issuing the password unlock command, while asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a the ?freeze state?. if the password protection mode lock bit is not programmed, the device defaults to persistent protection mode. in the persistent protection mode, the ppb lock bit is cleared to the ?unfreeze state? after power-up or hardware reset. the ppb lock bit is set to the ?freeze state? by issuing the ppb lock bit set command. once set to the ?freeze state? the only means for cl earing the ppb lock bit to the ?unfreeze state? is by issuing a hardware or power-up reset. the password unlock com- mand is ignored in persistent protection mode. reading the ppb lock bit requires a 200ns access time. secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 bytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. the factory offers the device with the secsi sector either customer lockable (standard shipping option) or factory locked (contact an amd sales representa- tive for ordering information). the customer-lockable version is shipped with the secsi sector unprotected, allowing customers to program the sector after receiv- ing the device. the customer-lockable version also has the secsi sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? thus, the secsi sector indicator bit prevents customer- lockable devices from being used to replace devices that are factory locked. note
52 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information that the acc function and unlock bypass modes are not available when the secsi sector is enabled. the secsi sector address space in this device is allocated as follows: the system accesses the secsi sector through a command sequence (see ?write protect (wp#)?). after the system has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the de- vice. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secsi sector not programmed or protected at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming com- mand sequence. see command definitions. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2 , ex- cept that reset# may be at either v ih or v id . this allows in-system protec- tion of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. ? to verify the protect/unprotect status of the secsi sector, follow the algo- rithm shown in figure 1 . once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequ ence to return to reading and writing within the remainder of the array. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on ordering esn factory locked devices. customers may opt to have their code programmed by the factory through the expressflash service (express flash factory locked). the devices are then shipped from the factory with the secsi sector permanently locked. contact your sales representative for details on using the expressflash service. secsi sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 53 advance information write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector group without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in?ad- vanced sector protection? section on page 46. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is in- creased. see the table in ?dc characteristics? section on page 86. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or un- protected using the method describe d in ?sector group protection and unprotection?. note that wp# has an internal pullup; when uncon- nected, wp# is at v ih . hardware data protection the command sequence requirement of unl ock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 16 and 17 for command definitions). in addition, the fo llowing hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can
54 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information then be device-independent, jedec id -independent, and forward- and back- ward-compatible for the specified flas h device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 8-11. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 8?11. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alter- natively, contact your sales representative for copies of these documents.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 55 advance information ta b l e 8 . cfi query identification string table 9. system interface string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h typical timeout per single byte/word write 2 n s 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h max. timeout for byte/word write 2 n times typical 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
56 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ta b l e 1 0 . device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 001ah 0019h 0018h device size = 2 n byte 1a = 512 mb, 19 = 256 mb, 18 = 128 mb 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 0000h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 00ffh, 001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb 31h 32h 33h 34h 60h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 57 advance information ta b l e 1 1 . primary vendor-specific extended query command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 12 and table 13 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteri stics section for timing diagrams. addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0100b = 110 nm mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0008h sector protect/unprotect scheme 0008h = advanced sector protection 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 00xxh wp# protection 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported
58 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same ex- ception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations sec- tion for more information. the read-only operations??ac characteristics? section on page 88 provides the read pa rameters, and figure 11 shows the timing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequen ce is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a wr ite buffer programming operation, the sys- tem must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to access the manu- facturer and device codes, and determine whether or not a sector is protected. ta b l e 12 and table 13 show the address and data requirements. this method is an alternative to that shown in table 5 , which is intended for prom programmers
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 59 advance information and requires v id on address pin a9. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: ? a read cycle at address xx00h returns the manufacturer code. ? three read cycles at addresses 01h, 0eh, and 0fh return the device code. ? a read cycle to an address containing a sector address (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. the system must write the reset command to return to the read mode (or erase- suspend-read mode if the device was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word/16- byte random electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector com- mand sequence returns the device to normal operation. table 12 and table 13 show the address and data requirements for both command sequences. see also ?secsi (secured silicon) sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con- trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 12 and table 13 show the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. refer to the write op- eration status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. note that a hard- ware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence of address locations and across sector boundaries. programming to the same word address multiple times without in- tervening erases (incremental bit programming) requires a modified programming method. for such applicatio n requirements, please contact your local spansion representative. word programming is supported for backward
60 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information compatibility with existing flash driver software and for occassional writng of in- dividual words. use of write buffer programming is strongly recommended for general programming use when more than a few words are to be programmed. the effective word programming time using write buffer programming is much shorter than the single word programming time. any word cannot be pro- grammed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program words to the device faster than using the standard progra m command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and da ta. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 12 and table 13 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock by- pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 12 and table 13 ). write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming will occur. the fourth cycle writes the sec- tor address and the number of word locations, minus one, to be programmed. for example, if the system will program 6 uni que address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/ data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer loca- tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer pages. this also means that write buffer program- ming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort.)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 61 advance information note that if a write buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming oper- ation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence ca n be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one se- lected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset com- mand sequence must be written to reset the device for the next operation. note that the full 3-cycle write-to-buffer-abort reset command sequence is required when using write-buffer-programming features in unlock bypass mode. write buffer programming is allowed in any sequence. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. this flash device is capable of handling multiple write buffer program- ming operations on the same write buffer address range without intervening erases. for applications requiring incremental bit programming, a modified pro- gramming method is required, please contact your local spansion representative. any bit in a write buffer address range cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. how- ever, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? accelerated program the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not
62 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information be at v hh for operations other than accelerated programming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . figure 3 illustrates the algorithm for the program operation. refer to the erase and program operations??ac characteristics? section on page 88 section for pa- rameters, and figure 14 for timing diagrams.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 63 advance information figure 1. write buffer prog ramming operation write ?write to buffer? command and sector address write number of addresses to program minus 1(wc) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pa s s read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. (note 1) (note 2) (note 3) notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write- buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see tables 16 and 17 for command sequences required for write buffer programming.
64 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information figure 2. program operation program suspend/prog ram resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programmin g operation so that data can be read from any non-suspended sector. when the program suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not re- quired when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper co mmand sequences to enter and exit this region. note that the secsi sector autoselect, and cfi functions are unavailable when program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 12 and table 13 for program com- mand sequence.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 65 advance information after the program resume command is written, the device reverts to program- ming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write op- eration status for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ignored. another program suspend command can be written after the device has resume programming. figure 3. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. table 12 and table 13 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for information on these status bits. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
66 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information any commands written during the chip erase operation are ignored, including erase suspend commands. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to en- sure data integrity. figure 4 illustrates the algorithm for the erase operation. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase op- eration in is progress. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. table 12 and table 13 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em- bedded erase algorithm automatically prog rams and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure al l commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com- mand other than sector erase or erase suspend during the time-out period resets the device to the read mode. note that the secsi sector, autoselect, and cfi functions are una vailable when an erase operation in is progress. the system must rewrite the command sequence and any addi- tional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated on ce the device has returned to reading array data, to ensure data integrity. figure 4 illustrates the algorithm for the erase operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 16 section for timing diagrams.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 67 advance information figure 4. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, includ- ing the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase suspend command is written during the sec- tor erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-sus- pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta- tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. the system can determine the status of the pro- start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 12 and table 13 for program command sequence. 2. see the section on dq3 for information on the sector erase timer.
68 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information gram operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. refer to the autoselect mode section and ?autoselect command sequence? section on page 58 sections for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspen ded sector is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. it is important to allow an intervalof at least 5 ns between erase resume and erase suspend. lock register command set definitions the lock register command set permits the user to one-time program the secsi sector protection bit, persistent protection mode lock bit, and password protec- tion mode lock bit. the lock register bits are all readable after an initial access delay. the lock register command set entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. note that issuing the lock register command set entry command disables reads and writes for the flash memory . ? lock register program command ? lock register read command the lock register command set exit command must be issued after the ex- ecution of the commands to reset the device to read mode. otherwise the device will hang. if this happens, the flash device must be reset. please refer to reset# for more information. it is important to note that the device will be in either per- sistent protection mode or password protection mode depending on the mode selected prior to the device hang. for either the secsi sector to be locked, or the device to be permanently set to the persistent protection mode or the password protection mode, the associated lock register bits must be programmed. note that the persistent protection mode lock bit and password protection mode lock bit can never be pro- grammed together at the same time. if so, the lock register program operation will abort . the lock register command set exit command must be initiated to re- enable reads and writes to the main memory. password protection command set definitions the password protection command set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. the password protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the password protection command set entry command disabled reads and writes the main memory.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 69 advance information ? password program command ? password read command ? password unlock command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. there is no special addressing order required for programming the pass- word. the password is programmed in 8-bit or 16-bit portions. each portion requires a password program command. once the password is written and verified, the password protection mode lock bit in the ?lock register? must be programmed in order to prevent verification. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm tm with the cell remaining as a ?0?. the password is all f?s when shipped from the factory. all 64-bit password combinations are valid as a password. the password read command is used to verify the password. the password is verifiable only when the password protection mode lock bit in the ?lock register? is not programmed. if the password protection mode lock bit in the ?lock regis- ter? is programmed and the user attempts to read the password, the device will always drive all f?s onto the dq databus. the lower two address bits (a1?a0) for word mode and (a1?a-1) for by byte mode are valid during the password read, password program, and password un- lock commands. writing a ?1? to any other address bits (a max -a2) will abort the password read and password program commands. the password unlock command is used to clear the ppb lock bit to the ?unfreeze state? so that the ppb bits can be modi fied. the exact password must be entered in order for the unlocking function to occur. this 64-bit password unlock com- mand sequence will take at least 2 s to process each time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match the password. if another password unlock is issued before the 64-bit password check execution window is completed, the command will be ignored. if the wrong address or data is given during password unlock command cycle, the device may enter the write-to- buffer abort state. in order to exit the write-to-abort state, the write-to- buffer-abort-reset command must be given. otherwise the device will hang. the password unlock function is accomplished by writing password unlock com- mand and data to the device to perform the clearing of the ppb lock bit to the ?unfreeze state?. the password is 64 bits long. a1 and a0 are used for matching in word mode and a1, a0, a-1 in byte mode. writing the password unlock com- mand does not need to be address order specific. an example sequence is starting with the lower address a1-a0=00, followed by a1-a0=01, a1-a0=10, and a1-a0=11 if the device is configured to operate in word mode. approximately 2 s is required for unlocking the device after the valid 64-bit password is given to the device. it is the responsibility of the mi- croprocessor to keep track of the entering the portions of the 64-bit password with the password unlock command, the order, and when to read the ppb lock bit to conf irm successful password unlock. in order to re-lock the device into the password protection mode, the ppb lock bit set com- mand can be re-issued.
70 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information the password protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. otherwise the device will hang. note that issuing the password protection command set exit command re- enables reads and writes for the main memory. non-volatile sector protection command set definitions the non-volatile sector protection command set permits the user to program the persistent protection bits (ppb bits), erase all of the persistent protection bits (ppb bits), and read the logic state of th e persistent protection bits (ppb bits). the non-volatile sector protection command set entry command se- quence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the non-volatile sector protection command set entry command disables reads and writes for the main memory . ? ppb program command the ppb program command is used to program, or set, a given ppb bit. each ppb bit is individually programmed (but is bulk erased with the other ppb bits). the specific sector address (a24-a16 for S29GL512N, a23-a16 for s29gl256n, a22- a16 for s29gl128n) is written at the same time as the program command. if the ppb lock bit is set to the ?freeze state?, the ppb program command will not exe- cute and the command will time-out without programming the ppb bit. ? all ppb erase command the all ppb erase command is used to erase all ppb bits in bulk. there is no means for individually erasing a specific ppb bit. unlike the ppb program, no spe- cific sector address is required. however, when the all ppb erase command is issued, all sector ppb bits are erased in parallel. if the ppb lock bit is set to ?freeze state?, the all ppb erase command will not execute and the command will time-out without erasing the ppb bits. the device will preprogram all ppb bits prior to erasing when issuing the all ppb erase command. also note that the total number of ppb program/erase cycles has the same endurance as the flash memory array. ? ppb status read command the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device. this requires an initial access time latency. the non-volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the non-volatile sector protection command set exit command re-enables reads and writes for the main memory . global volatile sector protection freeze command set the global volatile sector protection freeze command set permits the user to set the ppb lock bit and reading the logic state of the ppb lock bit. the global volatile sector protection freeze command set entry com- mand sequence must be issued prior to any of the commands listed following to enable proper command execution.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 71 advance information reads and writes from the main memory are allowed. ? ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit to the ?freeze state? if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set to the ?freeze state?, it cannot be cleared unless the device is taken through a power-on clear (for persistent protection mode) or the password unlock command is executed (for password protection mode). if the password protection mode lock bit is programmed, the ppb lock bit status is reflected as set to the ?freeze state?, even after a power-on reset cycle. ? ppb lock bit status read command the programming state of the ppb lock bit can be verified by executing a ppb lock bit status read command to the device. the global volatile sector protection freeze command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. volatile sector protection command set the volatile sector protection command set permits the user to set the dynamic protection bit (dyb) to the ?protected state?, clear the dynamic protection bit (dyb) to the ?unprotected state?, and read the logic state of the dynamic protec- tion bit (dyb). the volatile sector protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the volatile sector protection command set entry com- mand disables reads for the bank selected with the command . reads and writes for other banks exclud ing that bank are allowed . ? dyb set command ? dyb clear command the dyb set and dyb clear commands are used to protect or unprotect a dyb for a given sector. the high order address bits are issued at the same time as the code 00h or 01h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dyb bits are modifiable at any time, regardless of the state of the ppb bit or ppb lock bit. the dyb bits are cleared to the ?unprotected state? at power-up or hardware reset. ?dyb status read command the programming state of the dyb bit for a given sector can be verified by writing a dyb status read command to the device. this requires an initial access delay. the volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the volatile sector protection command set exit com- mand re-enables reads and writes to the main memory . secsi sector entry command the secsi sector entry command allows the following commands to be executed ? read from secsi sector
72 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ? program to secsi sector once the secsi sector entry command is issued, the secsi sector exit command has to be issued to exit secsi sector mode. secsi sector exit command the secsi sector exit command may be issued to exit the secsi sector mode.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 73 advance information command definitions ta b l e 1 2 . S29GL512N, s29gl256n, s29gl128n command definitions, x16 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1 ra rd reset (7) 1 xxx f0 autoselect (note 8) manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id 4 555 aa 2aa 55 555 90 x01 227e x0e note 17 x0f note 17 sector protect verify 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 secure device verify (9) 4 555 aa 2aa 55 555 90 x03 note 10 cfi query (11) 1 55 98 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer 3 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (16) 3 555 aa 2aa 55 555 f0 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (12) 2 xxx a0 pa pd unlock bypass sector erase (12) 2 xxx 80 sa 30 unlock bypass chip erase (12) 2 xxx 80 xxx 10 unlock bypass reset (13) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend/program suspend (14) 1 xxx b0 erase resume/program resume (15) 1 xxx 30 sector command definitions secsi tm sector secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit (18) 4 555 aa 2aa 55 555 90 xx 00 lock register command set definitions lock register lock register command set entry 3 555 aa 2aa 55 555 40 lock register bits program (22) 2 xxx a0 xxx data lock register bits read (22) 1 00 data lock register command set exit (18, 23) 2 xxx 90 xxx 00 password protection command set definitions
74 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information legend: x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on th e rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. password password protection command set entry 3 555 aa 2aa 55 555 60 password program (20) 2 xxx a0 pwa x pwd x password read (19) 4 xxx pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 password unlock (19) 7 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 password protection command set exit (18, 23) 2 xxx 90 xxx 00 non-volatile sector protection command set definitions ppb nonvolatile sector protection command set entry 3 555 aa 2aa 55 555 c0 ppb program (24, 25) 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb status read (25) 1 sa rd (0) non-volatile sector protection command set exit (18) 2 xxx 90 xxx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global non-volatile sector protection freeze command set entry 3 555 aa 2aa 55 555 50 ppb lock bit set (25) 2 xxx a0 xxx 00 ppb lock status read (25) 1 xxx rd (0) global non-volatile sector protection freeze command set exit (18) 2 xxx 90 xxx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry 3 555 aa 2aa 55 555 e0 dyb set (24, 25) 2 xxx a0 sa 00 dyb clear (25) 2 xxx a0 sa 01 dyb status read (25) 1 sa rd (0) volatile sector protection command set exit (18) 2 xxx 90 xxx 00 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 75 advance information wc = word count is the number of write buffer locations to load minus 1. pwd = password pwd x = password word0, word1, word2, and word3. data = lock register contents: pd(0) = secsi sector protection bit, pd(1) = persistent protection mode lock bit, pd(2) = password protection mode lock bit. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don't cares for unlock and command cycles. 5. address bits a max :a16 are don't cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autosele ct mode, or if dq5 goes high (while the device is providing status data). 8. the fourth, fifth, and sixth cycle of the au toselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. this is same as ppb status read except th at the protect and unprotect statuses are inverted here. 10. the data value for dq7 is ?1? for a serialized and protected otp region and ?0? for an unserialized and unprotected secsi?sector region. see "secsi?sector flash memory region? for more information. for s29glvxxxnh: xx18h/18h = not factory locked. xx98h/98h = factory locked. for s29glxxxnl: xx08h/08h = not factory locked. xx88h/88h = factory locked. 11. command is valid when device is ready to read a rray data or when device is in autoselect mode. 12. the unlock-bypass command is required pr ior to the unlock-bypass-program command. 13. the unlock-bypass-reset command is required to return to reading array data when the device is in the unlock bypass mode. 14. the system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 15. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 16. issue this command sequence to return to read mode after detecting device is in a write-to-buffer-abort state. note: the full command sequence is required if resettin g out of abort while using unlock bypass mode. 17. S29GL512Nh/l = 2223h/23h, 220h/01h; s29gl256nh/l = 2222h/22h, 2201h/01h; s29gl128nh/l = 2221h/21h, 2201h/ 01h. 18. the exit command returns the device to reading the array. 19. note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 20. for pwdx, only one portion of the password can be programmed per each ?a0? command. 21. the all ppb erase command embeds programming of all ppb bits before erasure. 22. all lock register bits are one-time programmable. note that the program state = ?0? and the erase state = ?1?. also note that of both the persistent protection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation will abort and return the device to read mode. lock register bits that are reserved for future use will default to ?1's?. the lock regist er is shipped out as ?ffff's? before lock register bit progra m execution. 23. if any of the entry command was initiated, an exit command mu st be issued to reset the device into read mode. otherwise the device will hang. 24. if acc = v hh , sector protection will match when acc = v ih 25. protected state = ?00h?, unprotected state = ?01h?.
76 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ta b l e 1 3 . S29GL512N, s29gl256n, s29gl128n command definitions, x8 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (6) 1 ra rd reset (7) 1 xxx f0 autoselect manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id 4 aaa aa 555 55 aaa 90 x02 xx7e x1c note 17 x1e note 17 sector protect verify 4 aaa aa 555 55 aaa 90 (sa) x04 00 01 secure device verify (9) 4 aaa aa 555 55 aaa 90 x06 note 10 cfi query (11) 1 aa 98 write to buffer 3 aaa aa 555 55 sa 25 sa wc pa pd wbl pd program buffer to flash (confirm) 1 sa 29 write-to-buffer-abort reset (16) 3 aaa aa pa 55 555 f0 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase suspend/program suspend (14) 1 xxx b0 erase resume/program resume (15) 1 xxx 30 secsi sector command definitions secsi tm sector secsi sector entry 3 aaa aa 555 55 aaa 88 secsi sector exit (18) 4 aaa aa 555 55 aaa 90 xx 00 lock register command set definitions lock register lock register command set entry 3 aaa aa 555 55 aaa 40 lock register bits program (22) 2 xxx a0 xxx data lock register bits read (22) 1 00 data lock register command set exit (18, 23) 2 xxx 90 xxx 00 password protection command set definitions password password protection command set entry 3 aaa aa 555 55 aaa 60 password program (20) 2 xxx a0 pwa x pwd x password read (19) 8 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 password unlock (19) 11 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 00 29 password protection command set exit (18, 23) 2 xxx 90 xxx 00
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 77 advance information legend: x = don?t care ra = address of the memory to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on th e rising edge of the we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a max ?a16 uniquely select any sector. wbl = write buffer location. the address must be within the same write buffer page as pa. wc = word count is the number of write buffer locations to load minus 1. pwd = password pwd x = password word0, word1, word2, word3. word 4, word 5, word 6, and word 7. data = lock register contents: pd(0) = secsi sector protection bit, pd(1) = persistent protection mode lock bit, pd(2) = password protection mode lock bit. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle, and the 4th, 5th, and 6th cycle of the autoselect command sequence, all bus cycles are write cycles. non-volatile sector protection command set definitions ppb nonvolatile sector protection command set entry 3 aaa aa 55 55 aaa c0 ppb program (24, 25) 2 xxx a0 sa 00 all ppb erase 2 xxx 80 00 30 ppb status read (25) 1 sa rd (0) non-volatile sector protection command set exit (18) 2 xxx 90 xxx 00 global non-volatile sector protection freeze command set definitions ppb lock bit global non-volatile sector protection freeze command set entry 3 aaa aa 555 55 aaa 50 ppb lock bit set (25) 2 xxx a0 xxx 00 ppb lock status read (25) 1 xxx rd (0) global non-volatile sector protection freeze command set exit (18) 2 xxx 90 xxx 00 volatile sector protection command set definitions dyb volatile sector protection command set entry 3 aaa aa 555 55 aaa e0 dyb set (24, 25) 2 xxx a0 sa 00 dyb clear (25) 2 xxx a0 sa 01 dyb status read (25) 1 sa rd (0) volatile sector protection command set exit (18) 2 xxx 90 xxx 00 command (notes) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data
78 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information 4. data bits dq15-dq8 are don't cares for unlock and command cycles. 5. address bits a max :a16 are don't cares for unlock and command cycles, unless sa or pa required. (a max is the highest address pin.). 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data when device is in the autosele ct mode, or if dq5 goes high (while the device is providing status data). 8. the fourth, fifth, and sixth cycle of the au toselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a protected sector. see ?autoselect command sequence? for more information. this is same as ppb status read except th at the protect and unprotect statuses are inverted here. 10. the data value for dq7 is ?1? for a serialized and protected otp region and ?0? for an unserialized and unprotected secsi? sector region. see "secsi? sector flash memory region? for more information. for s29glxxxnh.: xx18h/18h = not factory locked. xx98h/98h = factory locked. for s29glxxxnl: xx08h/08h = not factory locked. xx88h/88h = factory locked. 11. command is valid when device is ready to read a rray data or when device is in autoselect mode. 12. the system may read and program/program suspend in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 13. the erase resume/program resume command is valid only during the erase suspend/program suspend modes. 14. issue this command sequence to return to read mode after detecting device is in a write-to-buffer-abort state. note: the full command sequence is required if resettin g out of abort while using unlock bypass mode. 15. S29GL512Nh/l = 2223h/23h, 220h/01h; s29gl256nh/l = 2222h/22h, 2201h/01h; s29gl128nh/l = 2221h/21h, 2201h/ 01h. 16. the exit command returns the device to reading the array. 17. note that the password portion can be entered or read in any order as long as the entire 64-bit password is entered or read. 18. for pwdx, only one portion of the password can be programmed per each ?a0? command. 19. the all ppb erase command embeds programming of all ppb bits before erasure. 20. all lock register bits are one-time programmable. note that the program state = ?0? and the erase state = ?1?. also note that of both the persistent protection mode lock bit and the password protection mode lock bit cannot be programmed at the same time or the lock register bits program operation will abort and return the device to read mode. lock register bits that are reserved for future use will default to ?1's?. the lock regist er is shipped out as ?ffff's? before lock register bit progra m execution. 21. if any of the entry command was initiated, an exit command mu st be issued to reset the device into read mode. otherwise the device will hang. 22. if acc = v hh , sector protection will match when acc = v ih protected state = ?00h?, unprotected state = ?01h?. write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 19 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. note that all write operation status dq bits are valid only after 4 s delay. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com- plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro-
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 79 advance information gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is as- serted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on successive read cycles. ta b l e 14 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 17 in the ac characteristics section shows the data# polling timing diagram.
80 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information figure 5. data# polling algorithm ry / b y # : r e a d y / bu s y # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 14 shows the outputs for ry/by#. dq7 = data? yes no no dq5 = 1 no yes yes fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 81 advance information dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy- cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approxi- mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e 14 shows the outputs for toggle bit i on dq6. figure 6 shows the toggle bit algorithm. figure 18 in the ?ac characteristics? section shows the toggle bit tim- ing diagrams. figure 19 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii.
82 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information figure 6. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 83 advance information read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 14 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# subsec- tion. figure 18 shows the toggle bit timing diagram. figure 19 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. whenever the system initially be- gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. altern atively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de- termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command.
84 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as- sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi- tional sector erase commands. to ensu re the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 14 shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort- reset command sequence to return the de vice to reading array data. see write buffer section for more details. ta b l e 1 4 . write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 85 advance information absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9, oe#, acc and reset# (note 2) . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v output short circuit current (note 3) 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to +3.6 v v io (note 2) . . . . . . . . . . . . . . . . . . . +1.65 v to +1.95 v or +2.7 to + 3.6 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see ordering information (256 mb) section for valid v cc /v io range combinations. the i/os will not operate at 3 v when v io =1.8 v. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
86 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than tbd ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program or write buffer programming is in progress. 3. not 100% tested. 4. automatic sleep mode enables the lower power mode when addresses remain stable tor t acc + 30 ns. 5. v io = 1.65?1.95 v or 2.7?3.6 v 6. v cc = 3 v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at 3v. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i io1 v io active read current (switching current) v io = 1.8 v, ce# = v il , oe# = v il , we# = v il , f = 5 mhz 510a i io2 v io non-active output ce# = v il, oe# = v ih 0.2 10 ma i cc1 v cc active read current (1) ce# = v il, oe# = v ih , v cc = v ccmax , f = 5 mhz, byte mode 25 30 ma ce# = v il, oe# = v ih , v cc = v ccmax , f = 5 mhz, word mode 25 30 i cc2 v cc initial page read current (1) ce# = v il, oe# = v ih, v cc = v ccmax 50 60 ma i cc3 v cc intra-page read curren t (1) ce# = v il, oe# = v ih, v cc = v ccmax 10 20 ma i cc4 v cc active erase/program current (2, 3) ce# = v il, oe# = v ih, v cc = v ccmax 50 70 ma i cc5 v cc standby current ce#, reset# = v ss 0.3 v, oe# = v ih, v cc = v ccmax v il = v ss + 0.3 v/-0.1v, 15a i cc6 v cc reset current v cc = v ccmax; v il = v ss + 0.3 v/-0.1v, reset# = v ss 0.3 v 15a i cc7 automatic sleep mode (4) v cc = v ccmax v ih = v cc 0.3 v, v il = v ss + 0.3 v/-0.1v, wp#/acc = v ih 15a i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v ccmax, wp#/acc = v ih wp#/acc pin 10 20 ma v cc pin 30 60 v il input low voltage (5) ?0.1 0.3 x v io v v ih input high voltage (5) 0.7 x v io v io + 0.3 v v hh voltage for acc erase/program acceleration v cc = 2.7 ?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.5 v v ol output low voltage (5) i ol = 100 a 0.15 x v io v v oh output high voltage (5) i oh = 100 a 0.85 x v io v v lko low v cc lock-out voltage (3) 2.3 2.5 v
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 87 advance information test conditions note: if v io < v cc , the reference level is 0.5 v io . key to switching waveforms note: diodes are in3064 or equivalent table 15. test specifications 2.7 k ? c l 6.2 k ? 3.3 v device under test note: diodes are in3064 or equivalent. figure 9. test setup test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels (see note) 0.5v io v output timing measurement reference levels 0.5 v io v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v 0.5 v io 0.5 v io v output measurement level input note: if v io < v cc , the input measurement reference level is 0.5 v io . figure 10. input waveforms and measurement levels
88 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics read-only operations?S29GL512N only notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 15 for test specifications. 5. unless otherwise indicated, ac specifications for 90 ns and 100 ns speed options are tested with v io = v cc = 3 v. ac specifications for 100 ns and 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 90 100 100 110 unit t avav t rc read cycle time v io = v cc = 3 v min 90 100 ns v io = 2.5 v, v cc = 3 v (note 1) 100 110 v io = 1.8 v, v cc = 3 v 100 110 ns t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 90 100 ns v io = 2.5 v, v cc = 3 v (note 1) 100 110 v io = 1.8 v, v cc = 3 v 100 110 ns t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 90 105 ns v io = 2.5 v, v cc = 3 v (note 1) 100 110 v io = 1.8 v, v cc = 3 v 100 110 ns t pac c page access time max 25 25 35 35 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t ceh chip enable hold time read min 35 ns
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 89 advance information ac characteristics read-only operations?s29gl256n only notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 15 for test specifications. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 80 90 90 100 unit t avav t rc read cycle time v io = v cc = 3 v min 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t pac c page access time max 25 25 35 35 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t ceh chip enable hold time read min 35 ns
90 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics read-only operations?s29gl128n only notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 15 for test specifications. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter description test setup speed options jedec std. 80 90 90 100 unit t avav t rc read cycle time v io = v cc = 3 v min 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 80 90 ns v io = 2.5 v, v cc = 3 v (note 1) 90 100 v io = 1.8 v, v cc = 3 v 90 100 ns t pac c page access time max 25 25 35 35 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns tceh chip enable hold time read min 35 ns
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 91 advance information ac characteristics * figure shows word mode. addresses are a2?a-1 for byte mode. figure 12. page read timings figure 11. read operation timings t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df t ceh a23 - a2 ce# oe# a2 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
92 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics hardware reset (reset#) note: not 100% tested. if ramp rate is equal to or faster than 1v/100s with a falling edge of the reset# pin initiated, the reset# pin needs to be held low only for 100s for power-up.. parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 1 ms t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 1 ms t rp reset# pulse width min 1 ms t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 13. reset timings
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 93 advance information ac characteristics erase and program operations ?S29GL512N only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns and 100 ns speed options are tested with v io = v cc = 3 v. ac specifications for 100 ns and 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 90 100 100 110 unit t avav t wc write cycle time (note 1) min 90 100 100 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
94 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics erase and program operations ?s29gl256n only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 95 advance information ac characteristics erase and program operations ?s29gl128n only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s
96 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics notes: 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 9 and table 15 for test specifications. oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 14. program operation timings acc t vhh v hh v il or v ih v il or v ih t vhh figure 15. accelerated program timing diagram
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 97 advance information ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status?. 2. these waveforms are for the word mode. figure 16. chip/sector erase operation timings
98 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics figure 17. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: 1. va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read cycle. 2. t oe for data polling is 45 ns when v io = 1.65 to 2.7 v and is 35 ns when v io = 2.7 to 3.6 v
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 99 advance information ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 18. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6 . figure 19. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
100 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics alternate ce# controlled erase and program operations ?S29GL512N only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns and 100 ns speed options are tested with v io = v cc = 3 v. ac specifications for 100 ns and 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 90 100 100 110 unit t avav t wc write cycle time (note 1) min 90 100 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s effective accelerated write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 101 advance information ac characteristics alternate ce# controlled erase and program operations ?s29gl256n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s effective accelerated write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec
102 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information ac characteristics alternate ce# controlled erase and program operations ?s29gl128n only notes: 1. not 100% tested. 2. see the ?ac characteristics? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 80 ns and 90 ns speed options are tested with v io = v cc = 3 v. ac specifications for 90 ns and 100 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. parameter speed options jedec std. description 80 90 90 100 unit t avav t wc write cycle time (note 1) min 80 90 90 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 45 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s effective accelerated write buffer program operation (notes 2, 4) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 1.0 sec
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 103 advance information ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 20. alternate ce# controlled write (erase/program) operation timings
104 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles, checkerboard pattern. 2. under worst case conditions of 90c, v cc = 3.0 v, 1,000,000 cycles. 3. effective write buffer specification is based upon a 16-word write buffer operation. 4. the typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. in the pre-programming step of the embedded erase algo rithm, all bits are programmed to 00h before erasure. 6. system-level overhead is the time required to execut e the two- or four-bus-cycle sequence for the program command. see table 17 for further information on command definitions. tsop pin and bga package capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 1 3.5 sec excludes 00h programming prior to erasure (note 5) chip erase time s29gl128n 128 256 sec s29gl256n 256 512 S29GL512N 512 1024 total write buffer time (note 3) 240 s excludes system level overhead (note 6) total accelerated effective write buffer programming time (note 3) 200 s chip program time s29gl128n 123 sec s29gl256n 246 S29GL512N 492 parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf c out output capacitance v out = 0 tsop 8.5 12 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 105 advance information physical dimensions ts056?56-pin standard thin small outline package (tsop) notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 4 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 5 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 6 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 7 lead coplanarity shall be within 0.10 mm as measured from the seating plane. 8 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.80 14.00 14.10 13.90 0.60 0.70 0.50 -8? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
106 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information physical dimensions laa064?64-ball fortified ball grid array (fbga)
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 107 advance information revision summary revision a (september 2, 2003) initial release. revision a+1 (october 16, 2003) global added laa064 package. distinctive characteristics, performance characteristics clarified fifth bullet information. added rtsop to package options. distinctive characteristics, software and hardware features clarified ?password sector protection? to ?advanced sector protection? connection diagrams removed note. ordering information modified package codes device bus operations, table 1 modified table, removed note. sector address tables all address ranges doubled in all sector address tables. sector protection lock register: corrected text to reflect 3 bits instead of 4. table 6, lock register: corrected address range from dq15-5 to dq15-3; re- moved dq4 and dq3; corrected dq15-3 lock register to don?t care. table 7, sector protection schemes: corrected sector states. command definitions table 12, command definitions, x16 nonvolatile sector protection command set entry second cycle address cor- rected from 55 to 2aa. legend: clarified pwdx, data notes: clarified note 19. table 13, command definitions, x8 password read and unlock addresses and data corrected. legend: clarified pwdx, data notes: clarified note 19. test conditions table 15, test specifications and figure 10, input waveforms and measurement levels: corrected input pulse levels to 0.0?vio; corrected input timing mea- surement reference levels to 0.5v io .
108 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information revision a+2 (january 22, 2004) lock register corrected and added new text for secsi sector protection bit, persistent protec- tion mode lock bit, and password protection mode lock bit. persistent sector protection persistent protection bit (ppb): added the second paragraph text about program- ming the ppb bit. persistent protection bit lock (ppb lock bit): added the second paragraph text about configuring the ppb lock bit, and fourth paragraph on autoselect sector protection verification. added ppb lock bit requirement of 200ns access time. password sector protection corrected 1 s (built-in delay for each password check) to 2 s. lock register command set definitions added new information for this section. password protection command set definitions added new information for this section. non-volatile sector protection command set definitions added new information for this section. global volatile sector protection freeze command set added new information for this section. volatile sector protection command set added new information for this section. secsi sector entry command added new information for this section. secsi sector exit command added new information for this section. revision a+3 (march 2, 2004) connection diagrams removed 56-pin reverse tsop diagram. ordering information updated the standard products for the s29gl512/256/128n devices and modi- fied the valid combinations tables. word program command sequence added new information to this section. lock register command set definitions added new information to this section. table 13 updated this table.
may 13, 2004 27631a4 s29glxxxn mirrorbittm flash family 109 advance information revision a+4 (may 13, 2004) global removed references to rtsop. distinctive characteristics removed 16-word/32-byte page read bu ffer from performance characteristics. changed low power consumption to 25 ma typical active read current and re- moved 10 ma typical intrapage active read current. ordering information changed formatting of pages. changed model numbers from 00,01,02,03 to 01, 02, v1, v2. table 1, ?device bus operations ? combined wp# and acc columns. table 8, ?cfi query identification string ?, table 9, ?system interface string ?, table 10, ?device geometry definition ?, and table 11, ?primary vendor-specific extended query added address (x8) column. word program command sequence added text to fourth paragraph. figure 1, ?write buffer programming operation,? added note references and removed dq15 and dq13. figure 3, ?program suspend/program resume,? changed field to read xxxh/b0h and xxxh/30h. password protection command set definitions replaced all text. table 12, ?S29GL512N, s29gl256n, s29gl128n command definitions, x16 ? changed the first cycle address of cfi query to 55. table 13, ?S29GL512N, s29gl256n, s29gl128n command definitions, x8 ? changed the third cycle data device id to 90. removed unlock bypass reset. removed note 12 and 13. figure 5, ?data# polling algorithm,? removed dq15 and dq13. absoulte maximum ratings removed vcc from ?all other pins? with respect to ground. cmos compatible changed the max of i cc4 to 70 ma added v il to the test conditions of i cc5 , i cc6 , and i cc7 change the min of v il to - 0.1 v. updated note 5. read-only operations?s29gl128n only added t ceh parameter to table.
110 s29glxxxn mirrorbittm flash family 27631a4 may 13, 2004 advance information figure 11, ?read operation timings,? added t ceh to figure. figure 12, ?page read timings,? change a1-a0 to a2-a0. erase and program operations updated t whwh1 and t whwh2 with values. figure 16, ?chip/sector erase operation timings,? changed 5555h to 55h and 3030h to 30h. figure 17, ?data# polling timings (during embedded algorithms),? removed dq15 and dq14-dq8 added note 2 figure 18, ?toggle bit timings (during embedded algorithms),? changed dq6 & dq14/dq2 & dq10 to dq2 and dq6. alternate ce# controlled erase and program operations updated t whwh1 and t whwh2 with values. latchup characteristics removed table. erase and programming performance updated tbd with values. updated note 1 and 2. physical dimensions removed the reverse pinout information and note 3. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by fasl llc. fasl llc reserves the right to chang e or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, ex press, implied, or statutory. fasl llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 fasl llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressflash are trademarks of fasl llc. other company and pr oduct names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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